Hitachi, Ltd.

Patrick Hamilton

Masato Ishii

Masaaki Iwasaki

Tatsuo Higuchi

Junji Nakagoshi

Toshimitsu Ando

Hiromitsu Maeda

Yusuke Fukumura

Hidenori Kosugi

Masaya Nakahata

Takahiro Ogimoto

Takashi Oomori

The adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent of intermediate value and the mantissa having the minimum exponent of 2n+3 bits and adjusting digits and the mantissa having the maximum exponent, which reduces the mantissas from three to two terms, which carries out addition on the mantissas of the two terms, a normalization circuit which makes left shift so that the most significant bit becomes 1, a rounding circuit which uses an (n+3)th bit from the most significant bit as a new sticky bit, takes logical OR with the lower bits and performs rounding and an exponent operation unit which outputs a final exponent.

Three-term input floating-point adder-subtractor

A parallel processor system has a plurality of nodes interconnected by a network for communication under control of a network interface controller of each node. The network interface controller includes a message reception controller for receiving a message from another node and judging illustratively the status of message reception and the need to return an acknowledge message; an acknowledge generating unit for generating an acknowledge message transmission request based on predetermined information in the message and the reception status when the return of an acknowledge message is judged to be necessary; and a message transmission controller for receiving an acknowledge the message transmission request and generating and returning an acknowledge message correspondingly. At the receiving node, the network interface controller can return an acknowledge message without processor intervention.

Parallel processor

A computer system having a plurality of processing nodes interconnected by a message transfer network. Each node includes an instruction processor, a transmit circuit to transmit messages to other processing nodes through the message transfer network and a plurality of postings in a memory storage. Each message includes a header part and a data part with the header part having distinguishing fields that are used to distinguish messages. Each posting includes message specification fields corresponding to each distinguishing field of a message header part wherein the message specification fields selectively matching the distinguishing fields of a message. Each posting further includes a posted control field wherein the posted control field is used to control the operation of a receive circuit with respect to a message matching the posting. The receive circuit enables receiving of messages sent by other processing nodes through the network, searching upon reception of each message for and locating a posting having message specification fields that match the corresponding distinguishing fields of the message being received and to control upon location of a posting, the posted control field to control the operation of the receive circuit with respect to the message being received.

Computer system including a plurality of nodes for transferring through

To reduce an overhead of the interrupt on a processor associated with packet send and receive control in a network, a packet send command chaining unit is provided. Based on the control field in each packet send command, a send node controls an interrupt request to the processor in the packet level and sends a packet set with the control information to a receive node. Based on the control field in the received data packet, the receive node controls a receive circuit interrupt request, thereby reducing the number of times the interrupt on the instruction processor is caused for each packet send and receive operation.

Method and apparatus in a computer system having plural computers which

A crossbar switch and a broadcast communication method for use in a parallel computer that avoids an occurrence of deadlock states caused by conflicts for use of a path by a plurality of broadcast messages. The parallel computer, in which a plurality of nodes are connected by a crossbar switch, is provided with output buffer monitoring circuits. A vacant capacity of each of the output buffers is monitored. The vacant capacity of each output buffer is monitored to ensure that it is sufficiently high to store the broadcast message. The parallel computer is also provided with a priority controller in which one of a plurality of broadcast messages is selected when they are input. The message transmission-permit signal is issued to the packet selector circuits only when the broadcast transmission-permit signals for all the output ports for transmitting the message are issued. The broadcast transmission-permit signals are issued only when the vacant capacity of each output buffer is sufficiently high to store a broadcast message.

Crossbar switch system for always transferring normal messages and

In a parallel processor system, a plurality of nodes each comprising a processor and a main storage unit are interconnected through a network, wherein a user process is executed under the control of an operating system in each of the nodes and inter-process communications are performed through the network for transmitting and receiving messages among the nodes. Reception buffers are provided in a main storage unit and addressed by pool pages, which are discontinuous in a logical address domain or in a real address domain, in a virtual space used by the user process executed by each node. Additionally, reception buffer control information is located on the main storage unit for managing the reception buffers. A node, when receiving a message, uses communication information included in the received message and reception buffer control information to calculate a real address in the reception buffers for storing the received message.

Transferring messages in a parallel processing system using reception

A multistage interconnection network capable of performing highly reliable communications with less hardware. In the multistage interconnection network for interconnecting a plurality of nodes, the first and final stages each have switches two times as large as the number of switches at an intermediate stage. Two output ports of each node are connected to the input ports of different first stage switches, and two input ports are connected to the output ports of final stage different switches. The input ports of switches of the intermediate stage are connected to the output ports of first stage different switches, and the output ports are connected to the input ports of final stage different switches. At least one output port of each switch at the first stage is directly connected to at least one input port of an optional switch at the final stage.

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Machida, Japan

Patrick Hamilton