International Business Machines Corporation

Patrick H Buffet

Timothy W Budell

Yu H Sun

Charles S Chiu

Craig P Lussier

Danny Marvin Neal

Jean Audet

Paul Lee Clouser

Alain Caron

Joseph Natonio

Leah M P Pastel

Douglas C Heaberlin

Robert A Proctor

Louis L Hsu

Joseph N Kozhaya

John Maxwell Cohn

Susan K Lichtensteiger

Ivan L Wemple

Douglas Wayne Kemerer

Brian Joel Schuh

Thomas R Bednar

Erich C Schanzenbach

James V Crain, Jr

Paul E Dunn

Gulsun Yasar

Jon David Garlett

Kevin Grosselfinger

Donald S Kent

William F Smith

Esmaeil Rahmati

Gustina B Collins

Paul D Montane

William Smith

An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the substrate, for each electrical network. All of the first ports are electrically isolated from one another. All of the second ports are electrically connected to a common voltage. A computer readable program code, which is executed by a processor of a computer system computes for a first electrical network of the at least one electrical network an electrical resistance between each first port and a port of the second ports. The computer code may also display a perspective plot of the computed electrical resistances as a bar oriented about normal to each first port.

Validation of electrical performance of an electronic package prior to fabrication

An integrated circuit chip having a contact layer that includes a plurality of Vdd, Vddx, ground and I/O contacts arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. A multilayer X-Y power grid is located beneath the contact layer. A wiring layer is interposed between the contact layer and power grid to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires located alternatingly with one another. The Vddx wires are discontinuous between adjacent quadrants so that the magnitude of Vddx may be different in each quadrant of the chip if desired.

Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid

A method for improving the signal-to-noise ratio in an Idefect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An Idefect is activated to generate Idefect current within the integrated circuit. An amount of Idefect current generated within each area is measured at the terminals provided thereto. Based on the Icurrent measurement on each area, an Icurrent map is created. By analyzing the Icurrent map, the presence and location of the defect is determined. Based on the determination, the Idefect is isolated.

[object Object]

A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.

Apparatus and method to reduce signal cross-talk

The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.

Concurrent electrical signal wiring optimization for an electronic package

Disclosed is an improved method of determining mutual inductance of wires in an electronic design. First, the invention selects a pair of wires. Then, the invention adds concentric ring lines to the design. The invention then adds straight line segments representing each wire between points where each corresponding wire crosses the adjacent ring lines. Each of the straight lines run from a point where a corresponding wire crosses an outer concentric ring line to a point where the corresponding wire crosses an inner concentric ring line. The invention can then very simply calculate the mutual inductance between the straight line segments (not the actual potentially non-linear wires themselves). The mutual inductance of the straight line segments only comprises an approximate mutual inductance of the wires because the actual mutual inductance of the wires may be slightly different if the wires are non-linear.

Efficient and comprehensive method to calculate IC package or PCB trace mutual inductance using circular segments and lookup tables

An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of (and evenly spaces) the power switches according to the size of the serviceable area to which each of the power switches can provide power. The size of the power switches are matched to the current and voltage that will be provided by the power buses. The size of the serviceable area to which each of the power switches can provide power is dependent upon the size of the power switches.

Power switch circuit sizing technique

In the present invention an electronic package assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.

Electronic package having high density signal wires with low resistance

An electrical structure to optimize a signal wire structure. The electrical structure provides concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.

A method for improving the signal-to-noise ratio in an I defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An I defect is activated to generate I defect current within the integrated circuit. An amount of I defect current generated within each area is measured at the terminals provided thereto. Based on the I current measurement on each area, an I current map is created. By analyzing the I current map, the presence and location of the defect is determined. Based on the determination, the I defect is isolated.

Method for locating IDDQ defects using multiple controlled collapse chip connections current measurement on an automatic tester

A method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits. The method comprising: analyzing the voltage-island power distribution networks independently of the chip-level power distribution network to obtain voltage translation interface circuit currents; using the voltage translation interface circuit currents as input to a model of the chip-level power distribution network to obtain voltage translation interface circuit input voltages; and calculating voltage translation interface circuit output voltages based on the voltage translation interface circuit input voltages, the voltage translation interface circuit currents, and current-voltage characteristics of the voltage translation interface circuits.

Method of analyzing integrated circuit power distribution in chips containing voltage islands

An automated method of selecting differential pairs in an integrated circuit comprising loading the design database for the integrated circuit package, and selecting output parameters for the differential pairs comprises adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references. The method then includes comparing the output parameters to the design in the design database, and obtaining a resulting differential pairs list. The differential pair list preferably includes differential signal pairs having electrical characteristics within a predetermined design tolerance range. At least some of the differential signal pairs may comprise individual wires or connectors not physically adjacent one another.

Method for specifying, identifying, selecting or verifying differential signal pairs on IC packages

An electrical bus grid ( ) for an application specific integrated circuit (ASIC) chip ( ). The bus grid is generally formed by mutually orthogonal wires ( &prime;) contained within two metal layer (M &prime;, M &prime;). The bus grid is located within each of a plurality of contiguous rectangular regions ( &prime;), which are defined by electrical contacts ( &prime;). Due to the regular pattern of the electrical contacts, the bus grids within the contiguous rectangular regions are identical to one another, such that the bus grid forms a repeatable pattern. The widths of the wires in each of the two metal layers vary depending upon the magnitude of the current carried by the corresponding wire. The magnitude of the current in the power bus may be determined by simulation and modeling performed prior to placement of cells (e.g., ) within the ASIC chip.

Integrated circuit bus grid having wires with pre-selected variable widths

Disclosed is a method of designing voltage partitions in a solder bump package for a chip, comprising: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.

Growing community of inventors

Essex Junction, VT, United States of America

Patrick H Buffet