Northrop Grumman Systems Corporation

G-2 Networks, Inc.

Patrick G Farrell

Francis W Hopwood

Andrew J Piloto

Scott K Suko

Gary L Ferrell

Thomas R Turlington

Gregory K Sinon

Joseph A Faulkner

Gerald K Kane

William Pierce Evans

Eric Naviasky

Hao Tang

Anthony Caviglia

Hugh Thompson

John Monk, Jr

Jesus Chang

John Ebner

Robert R Angell

Joe Rocco

David Williams

A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.

Clock recovery circuit

A T/R module including a multilevel, multichip microwave package having a plurality of gallium arsenide monolithic microwave integrated circuit chips (MMICs) implementing RF switching elements, a variable phase shifter, a plurality of RF amplifiers, and gain trim attenuators and which are located on a planar RF assembly. The module's architecture includes shared or common MMIC circuit elements during both transmit and receive operation modes thus reducing the number of MMICs required while at the same time preloading the supply voltage regulator-modulator which supplies DC power to all the MMIC circuits without degrading T/R module efficiency.

Transmit/receive module for planar active apertures

An integrated circuit for use in a phased array antenna system having a central processing unit. The integrated circuit is associated with one of a plurality of antenna elements of the phased array antenna system. The integrated circuit includes an ID memory for storing a unique ID addressable by the central processing unit, and receives global commands from the central processing unit globally transmitted over a distributed serial bus. Upon detecting a global command, the integrated circuit compares an ID address associated with the global commands with the ID stored in the ID memory. The integrated circuit recognizes global commands as local commands to be executed locally when the ID address associated with the global commands is the same as the ID stored in the ID memory. In response to the local commands, the integrated circuit generates and provides control signals to the associated one of the antenna elements of the phased array antenna system.

Integrated circuit for remote beam control in a phased array antenna

Growing community of inventors

Baltimore, MD, United States of America

Patrick G Farrell