St-ericsson Sa

Patrick Fulcheri

Francois Chancel

Harald Bauer

Jean-Philippe Perrin

The method of protecting a secret key from being read by a non-secure software application, comprises a step () of recording the secret key as a routine stored in an executable-only memory. The routine having: load instructions to load the secret key into a memory readable by a secure and a non-secure software application, if the routine is called by the secure software application, and control instructions to leave only dummy data instead of the secret key in the readable memory if the software application calling the executable-only routine is the non-secure software application.

Secure terminal, a routine and a method of protecting a secret key

A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data. The data processing device (D) also comprises a configuration means (CM) coupled to the embedded processor (EP) and to the external memory interface (EMI) and arranged to deduce from at least one part of 8 bits of this N-bit data word (C), read by the external memory interface at the chosen address of the external memory (EM), the size and the Endian form of storage of the external memory, and to set the width of the external memory interface (EMI) according to the deduced external memory size and the data processing mode of the embedded processor (EP) according to the deduced Endian form of storage.

Data processing device adaptable to variable external memory size and endianess

A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C, C) coupled, via buses (BC, BC), to a memory (M) arranged to store data to be transferred between these cores (C, C). This control device (D) comprises at least one flag register (FR, FR) coupled to the cores (C, C) via the buses (BC, BC) and arranged to store, at Ni addresses, Ni flag values associated to data stored into the memory (M) by one of the cores and ready to be transferred towards the other core, each flag value stored at a first address being able to be set or reset by one of the cores (C, C) by means of a command designating the first address, thus authorizing another flag value stored at a second address to be simultaneously set or reset by the other core (C, C) by means of a command designating the second address.

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Antibes, France

Patrick Fulcheri