Intel Corporation

Patrick F Stolt

Thomas J Holman

Stephen S Pawlowski

Mark A Gonzales

A method and apparatus for an interface architecture for flexible and extensible media processing. In one embodiment, the apparatus may include on-chip interconnection logic, such as, for example, a crossbar. The apparatus, which in one embodiment is a chipset, may include at least one on-chip, functional unit, which is coupled to the interconnection logic. The at least one functional unit to operate as media processing stage of a media processing pipeline. In one embodiment, the apparatus may further include an on-chip controller to enable at least one selected off-chip functional unit to operate as a media processing stage of the media processing pipeline. Accordingly, in one embodiment, the chipset may provide an internal media processing pipeline, which may be expanded, reduced or modified by the inclusion of at least one off-chip media processing stage. Other embodiments are described and claimed.

Apparatus and method for an interface architecture for flexible and extensible media processing

A memory subsystem for a computer system includes a memory controller that has a data strobe generator. The memory subsystem further includes a Dynamic Random Access Memory (&ldquo;DRAM&rdquo;) array coupled to the memory controller and a data path coupled to the data strobe generator and the DRAM array. The DRAM array is separated into two DRAM sets coupled to a common output bus. Access to the DRAM array begins with access to the first DRAM set. After a first Column Address Strobe (CAS) is applied to the first DRAM set, a data strobe is asserted which causes data from the first DRAM set to be latched into the data path. On the next clock cycle after the data strobe is asserted, the data strobe and first CAS are de-asserted. A second CAS is then applied to the second DRAM set on the next clock cycle after the first CAS is de-asserted. In one embodiment, the data path includes a latch that has inputs coupled to the data strobe and an output of the DRAM array via the common output bus. In a further embodiment, the data path includes a flip-flop that has an input coupled to the latch output, and a clock input coupled to the clock.

Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage

The present invention provides a method and apparatus for automatically scrubbing ECC errors in memory upon the detection of a correctable error in data read from memory. This is performed by providing in a memory controller memory control logic for controlling accesses to memory, an ECC error checking and correcting unit for checking data read from memory for errors and correcting any correctable errors found in the read data, a first data buffer for storing the corrected read data output from the ECC error checking and correcting unit and a writeback path having an input end coupled to an output of the first data buffer and an output end coupled to memory. Upon the detection of a correctable error in data read from a particular memory location, the ECC error checking and correcting unit signals to the memory control logic the existence of a correctable error in the read data. The memory control logic then obtains exclusive control over the first data buffer and the writeback path to control writing of the corrected read data onto the writeback path and subsequently to memory.

Method and apparatus for automatically scrubbing ECC errors in memory

The present invention provides a method and apparatus in a memory controller coupled between a system bus and memory for independently supporting one of a Synchronous DRAM (SDRAM) and an Asynchronous DRAM (ADRAM) memory type via common signal pins. According to the preferred embodiment, the memory controller comprises memory control logic for generating both SDRAM and ADRAM memory interface signals and multiplexing means for selecting as output onto common signal pins either set of interface signals depending upon a memory type setting programmed within a configuration register. The memory control logic comprises at least a request processor in addition to two memory state machines, one for SDRAM and the other for ADRAM memory operations. When a system bus request is received by the request processor, it is assigned to a request state machine which interacts with both the SDRAM state machine and the ADRAM state machine to generate two sets of memory interface signals in addition to two sets of internal control signals. The sets of signals are input to a multiplexor provided for each type of control signals (i.e., memory interface and internal control), which multiplexors are controlled by the memory type select signal output from the configuration register. Based on the memory type setting programmed into the configuration registers, the appropriate sets of memory interface and internal control signals (i.e., either SDRAM or ADRAM) are selected for output to the memory array and to other units of the memory controller, respectively.

Memory controller for independently supporting Synchronous and

A method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller includes a memory controller having a data controller unit and a data path unit. Signals are passed between the data controller unit and the data path unit, thereby providing an interface between the two units. The data controller receives control signals from the bus and provides commands to the data path unit in response to these control signals. The commands provided to the data path unit enable the data path unit to transfer data to and from the bus and memory device.

Growing community of inventors

Beaverton, OR, United States of America

Patrick F Stolt