Advanced Micro Devices Corporation

Silicon Laboratories Inc.

Sigmatel, Inc.

Patrick Evan Maupin

Melanie D Typaldos

David Francis Tobias

Daniel B Reents

Charles Mitchell

Eric G Chambers

Thai H Pham

Dervinn Deyual Caldwell

Kenny Kok-Hoong Chiu

A memory includes an array of memory cells arranged in a plurality of rows and a plurality of columns. An address transform module receives a logical address including a logical column address and logical row address, and transforms the logical address into a physical address having a physical row address and a physical column address. An address decoder module accesses an individual memory cell of the array of memory cells based on the physical address.

Processing system, memory and methods for use therewith

A method for handling data transmissions within a modem is disclosed. A codeword is generated by compressing one or more incoming characters. The incoming characters and codeword are subsequently stored in a buffer. Then, a cost difference between transmitting all the codewords previously stored in the buffer and transmitting all the characters previously stored in the buffer is updated based on the most recent codeword. If the determined cost difference is less than a low limit value, the characters previously stored in the buffer are transmitted. However, if the determined cost difference is greater than a high limit value, the codewords previously stored in the buffer are transmitted. Otherwise, if the determined cost difference falls inclusively between the low limit value and the high limit value, transmission of the buffered data is deferred until the cost difference is recalculated on the next codeword.

Method for handling data transmissions within a modem

An integrated circuit such as a processor measures its own temperature with a temperature sensor. The measured temperature is compared to an upper limit value stored in the integrated circuit. An output terminal of the integrated circuit is asserted according to the comparison. In one mode of operation, the output terminal is asserted when the measured temperature is greater than the upper limit value and deasserted when the measured temperature goes below a lower limit value. A second output terminal is asserted when the temperature is above a second upper limit value, thereby indicating that temperature has exceeded a safe limit.

Method and apparatus for using an on-board temperature sensor on an integrated circuit

The present invention provides for an apparatus and a method for performing adaptive frame tracking. The present invention comprises an adaptive frame tracking unit capable of receiving and sending at least one data packet and automatically adjusting a data rate of the data packet by determining if there exists at least one data frame error and correcting for the data frame error in response to a determination that there exists at least one the data frame error.

Method and apparatus for adaptive frame tracking

A system adds functionality to a power button where use of the power button controls the entry and exit from a diagnostic mode. The system includes an information appliance connected to a diagnostic appliance. Once an information appliance is powered up, the information appliance monitors its power button for a press which indicates a request to enter a diagnostic mode. Absent a press of the power button, the system continues to be under control of the information appliance and never enters a diagnostic mode. However, if a press of the power button is detected, the system enters a diagnostic mode. Once in a diagnostic mode the system provides an exit therefrom by interpreting a power button press as a request to exit. The window of time to make such an exit closes once the diagnostic appliance achieves communication with the information appliance. If the power button is pressed during this window of time, then the system ends its diagnostic mode and control of the system returns to the information appliance. If the power button is pressed after the window of time has closed, then the diagnostic appliance retains control of the information appliance and maintains its ability to execute diagnostic type commands thereon. The illustrative system is particularly useful when incorporated into devices with limited interface connections such as legacy-free information appliances. The system allows for a standard existing button on the information appliance to serve diagnostic purposes, avoiding the need for initializing peripherals requiring substantial execution space.

Power button controlled diagnostic mode for an information appliance

A microcontroller is provided with one or more synchronous serial channels, such as HDLC channels, that are coupled to time slot assigners for communication over a time division multiplex bus. The time slot assigners each include a bit position start register and a bit position stop register that allows the time slot assigner to enable and disable the associated synchronous serial channel on the arrival of a specific bit position within the time division multiplex bus frame. Further, an end of slot adjust register provides for additional bits to be placed by the time slot assigner on to the end of a slot that is transmitted by an associated synchronous serial communication channel transmitter.

Flexible placement of serial data within a time divisioned multiplexed frame through programmable time slot start and stop bit positions

A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that can transmit a chained series of buffers without processor intervention. The buffers, however, include an interrupt on end-of-buffer flag that allows for an interrupt to be generated at the end of each buffer on a buffer-by-buffer basis.

Method and apparatus for generating interrupts on a buffer by buffer basis in buffer descriptor ring direct memory access system

A processor includes multiple register sets. A different register set may be dedicated to each of one or more interrupt sources, and yet another register set may be dedicated to other (non-interrupt) tasks. The interrupt sources may record interrupt service requests instead of signalling an interrupt to the processor. Periodically, the processor may poll the interrupt sources to determine if a service request is recorded.

Processor employing multiple register sets to eliminate interrupts

A microcontroller-based device according to the present invention provides a watchdog timer having an emulator support mode for disabling and reconfiguring time-outs. When the watchdog timer is placed in the emulator support mode, the watchdog timer is inhibited from counting. In a disclosed embodiment, the watchdog timer is inhibited from counting by deasserting a count enable signal. A watchdog time-out is thus prevented from occurring during the emulator support mode. Also, during the emulator support mode, the watchdog timer control register is writable, allowing the emulator to disable a watchdog timer, enable the timer, or program a new time-out value for the timer. The watchdog timer control register is writable regardless of the state of the enable bit of the timer. Further, in the emulator support mode, a watchdog timer current count becomes readable and writable at a predetermined register address above the watchdog timer control register subsequent to a write of a write key sequence to the watchdog timer control register. By writing and reading the predetermined register address location, the emulator is able to define and monitor a condition as the watchdog timer is approaching its timeout value. By monitoring a condition as the watchdog timer approaches its timeout value, a software debugger may better predict and appreciate the behavior of a microcontroller-based device prior to a watchdog time-out. In a disclosed embodiment, the watchdog timer current count is readable and writable through a watchdog timer count high register and a watchdog timer count low register.

Emulator support mode for disabling and reconfiguring timeouts of a

An asynchronous serial port having a control register and at least one data register exchanges data with a serial bus. The asynchronous serial port includes an indicator representing whether the data register contains all of the data bits, or whether some of the data may be stored in the control register. When a nine-bit data source (or any data source having more than eight bits of data) is received, the bits need not be divided among multiple registers, but can all be stored in the receive-data register. This is particularly useful during DMA or when the exchange of data has been suspended, for example by an interrupt, while additional frames may be received by the asynchronous serial port. Because frames are stored in a single register when an extended write bit or an extended read bit is set. Further, the receive data register also stores status bits associated with received data. This is especially useful during DMA operations, when status, including parity, frame, or overrun errors can be associated with a particular data item examining the stored DMA data itself.

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Austin, TX, United States of America

Patrick Evan Maupin