Cassy Holdings LLC

Taligent, Inc.

Silicon Graphics, Incorporated

The Directv Group, Inc.

Object Technology Licensing Corporation

Elxsi

Object Licensing Corporation

Patrick D Ross

Dave Olson

Bradley D Strand

Steven P Lemon

Matthew L Denman

David B Donahue

George W Norman

Steve H Milne

Benn Bollay

Robert A Olson

A system and method for aggregating data and for generating a stream of random numbers. There is a data bus, having a bus input with first and second output switching inputs that each mask values input thereto such that data from both the first and second output switching inputs are aggregated into the bus according to the masking thereof, and a bus output. There is also a data loop of random numbers having a data loop output port functionally coupled to the bus input through the first output switching input; a data feed having an output functionally coupled to the bus input through the second output switching input; and an active data operator coupled to the bus output such that data aggregated by the bus from the data loop and the first data feed is fed to the data operator, the output thereof being a stream of random numbers.

High clock-efficiency random number generation system and method

A system and method of generating a series of random number; from a source of random numbers in a computing system. Steps includes: loading a data loop (a looped array of stored values with an index) with random data from a source of random data; then repeating the following: reading a value from the data loop in relation to the index; operating on the multi-bit value thereby outputting a derived random number; and moving the index in relation to the looped array. The data loop may be a simple feedback loop which may be a shift register loaded by direct memory access (DMA). The operation may be performed by one or more arithmetic logic units (ALU) which may be fed by one or more data feeds and may perform XOR, Mask Generator, Data MUX, and/or MOD.

A system and method of generating a one-way function and thereby producing a random-value stream. Steps include: providing a plurality of memory cells addressed according to a domain value wherein any given domain value maps to all possible range values; generating a random domain value associated with one of the memory cells; reading a data value associated with the generated random domain value; generating dynamically enhanced data by providing an additional quantity of data; removing suspected non-random portions thereby creating source data; validating the source data according to a minimum randomness requirement, thereby creating a validated source data; and integrating the validated source data with the memory cell locations using a random edit process that is a masking, a displacement-in-time, a chaos engine, an XOR, an overwrite, an expand, a remove, a control plane, or an address plane module. The expand module inserts a noise chunk.

Modular uncertainty random value generator and method

A system, method, and device for stochastically processing data. There is an architect module operating on a processor configured to manage and control stochastic processing of data, a non-deterministic data pool module configured to provide a stream of non-deterministic values that are not derived from a function, a plurality of functionally equivalent data processing modules each configured to stochastically process data as called upon by the architect module, a data feed configured to feed a data set desired to be stochastically processed, and a structure memory module including a memory storage device and configured to provide sufficient information for the architect module to duplicate a predefined processing architecture and to record a utilized processing architecture.

Stochastic processing

A method of inserting chunks of bits into a target stream of bits within a computing system. The method includes the step of providing a target stream of bits. The method includes the step of providing a chunk stream of bits. The method includes the steps of chunking the chunk stream of bits into one or more chunks of bits; performing a random edit process on the target stream of bits by determining a random point within the target stream of bits and identifying random points within the target stream based on the mask stream until either the mask has no more insertion points or the target stream has no more bits.

System and method for inserting chunks of bits into a bit stream

Stochastic processing of an information stream by a processing architecture generated by operation of non-deterministic data used to select data processing modules

Uncertainty random value generator

A first publically routable IP address and a second publically routable IP address (bypass IP address) is firstly received from an Internet Service Provider (ISP) that forms part of a public network. An instruction to assign the second publically routable IP address to the host computer is then received. The first publically routable IP address is assigned to a Network Address Translation (NAT) service on the gateway and the second publically routable IP address is allocated to the host computer. Finally, the second publically routable IP address is allocated to the host computer. This allows the host computer to be configured to enable it to receive unsolicited packets from the public network through the gateway. A gateway and computer program product are also provided.

Apparatus and method for providing a globally routable bypass IP address to a host computer on a private network

The present invention comprises a method and system for peer to peer input output. The present invention is implemented on a computer system having a microprocessor and a packet switched router coupled to the microprocessor. The peer to peer input output system of the present invention defines a data source corresponding to a first device coupled to the computer system. The system then defines a data sink corresponding to a second device coupled to said computer system. The packet switch router is subsequently used to logically implement a data pipe between the data source and the data sink. The system configures the data pipe to provide adequate bandwidth between the data source and the data sink such that a data transfer occurs smoothly and predictably. The data transfer is performed via the data pipe such that the data transfer proceeds independently of any simultaneous second data transfer in the packet switched router.

Method and system for simultaneous high bandwidth input output

The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level. Thus, the system of the present invention ensures the first data transfer at the first priority level is not disturbed by the second data transfer. In this manner, the system of the present invention guarantees the first priority data transfer bandwidth for the software process.

System for communications where first priority data transfer is not

A method and apparatus for an innovative, object-oriented hardware independent interface to the external world. The interrupt services are part of an overall IO model providing an object base IO system that supports dynamic configuration of the system. Object processing is architected into even the lowest lever routines in the preferred embodiment of the invention. This includes an object oriented design all the way down to interrupt processing abstractions. These interrupt abstractions provide an architecturally sound framework for the dynamic installation, configuration, and timely execution of interrupt handlers.

Object oriented interrupt system

A hardware configuration system for enabling automatic configuration of hardware in a computer system. First, at system ipl, the particular computer system is identified based on its identification number. Then, a specific software component object is instantiated based on the computer system. All of the details of the standard computer system are predefined in the software component object based on supported hardware and peripherals for the specific hardware. Then a test is performed to determine if additional hierarchies are present. Each hierarchy has an associated identification number. If so, then for each hierarchy, the hierarchy is processed as discussed above. The result is a set of instantiated objects completely specifying the hardware environment.

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Sunnyvale, CA, United States of America

Patrick D Ross