Apple Inc.

Other

Patrick D McNamara

Toshinari Takayanagi

Jung Wook Cho

Anh T Hoang

Brian S Park

Michael G Frank

Douglas C Lee

Date Jan Willem Noorlag

Raman S Thiara

Geertjan Joordens

Alan R Gilchrist

John P Gonzalez

Kwang M Lee

Sung-Wook Kang

Meng C Chong

Craig A Pietrow

A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

Control scheme to temporarily raise supply voltage in response to sudden change in current demand

Control scheme to temporarily raise supple voltage in response to sudden change in current demand

A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.

Method and apparatus for power glitch detection in integrated circuits

A system and method for testing circuits. A generated input voltage waveform for a first phase of a test may use transitions with a voltage swing between expected low and high trigger points for an integrated circuit (IC) with hysteresis. A generated input voltage waveform for a second phase of the test may use transitions with a voltage swing between the expected low trigger point and a high sub-threshold value. The high sub-threshold value may be a tolerable voltage difference below the expected high trigger point. A generated input voltage waveform for a third phase of the test may use transitions with a voltage swing between the expected high trigger point and a low sub-threshold value. The low sub-threshold value may be a tolerable voltage difference above the expected low trigger point. The expected trigger points and sub-threshold values may be found from earlier characterization studies for the IC.

Method for testing integrated circuits with hysteresis

Monitoring aging information for multiple devices. Aging information of the devices may be received. Statistics regarding the multiple devices may be determined based on the aging information. For at least some of the devices, update information may be determined based on the respective aging information. The update information may include modifications to operating parameters of the devices. For example, the devices may operate according to initial parameters that are above sustainable parameters and the update information may lower the operating parameters based on the aging information.

Modifying operating parameters based on device use

In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated circuit may be booted, and the processor may execute the test programs from the memory. In one embodiment, the memory may also store a control program that may manage the execution of the tests. In an embodiment, the control program may also implement a protocol to communicate with the ATE to perform the testing. The protocol may be implemented over a set of general purpose input/output (I/O) pins, for example. Using the protocol and test vectors on the ATE, the tests may be selected and executed, and test results may be reported.

Test method using memory programmed with tests and protocol to communicate between device under test and tester

A system and method for fitting footwear and footwear inserts provides a removable insert which measures the foot by thermal imaging. The insert is provided with a thermally sensitive layer, for example a thermochromic material having a color transition interval within the range between room temperature and body temperature, that thus reacts to the heat transferred from portions of the foot in contact with the insert and temporarily changes color. The insert retains an image of the footprint for a short interval after contact with the foot, and can be removed from the footwear to examine the position and size of the foot relative to the footwear insole (and thus relative to the footwear) when the footwear is actually worn. For inserts which are purchased separately for cushioning, odor-reduction etc., the footprint image can be used as a guide to cut the footwear insert to follow the shape of an individual's foot.

Thermal imaging fitting system

Growing community of inventors

San Francisco, CA, United States of America

Patrick D McNamara