Koninklijke Philips Corporation N.V.

Patrick D Kelliher

Vasanth Reddy Gaddam

Dave Bryan

Monisha Ghosh

Viktor L Gornstein

Gennady Turkenich

An encoding system is configured to allow data to be transmitted at one of two selectable bit-error-rate quality factors. The first bit-error-rate quality factor selection corresponds to the conventional ATSC FEC encoding systems, and the second bit-error-rate quality factor selection provides an ATSC-like FEC encoding scheme that substantially improves the bit-error-rate. The first quality factor selection effects a 2/3 trellis encoding, whereas the higher quality factor selection effects a 1/3 trellis encoding. Because the high-quality trellis encoding rate of 1/3 is half the lower-quality trellis encoding rate of 2/3, the data rate of this high-quality encoded bit-stream is half that of the conventional lower-quality encoded bit-stream. The 1/3 trellis encoding is effected using an ATSC-compatible encoding and a modified symbol mapping. The encoding scheme provides 2:1 data redundancy and the symbol mapping provides a maximum distance for the redundant encoding. By combining techniques that each decrease the likelihood of an uncorrectable error at the receiver, the substantial improvement in bit-error-rate can be achieved. At the receiver, a single trellis decoder with different metric tables is used to decode the two bit-streams, thereby providing substantial compatibility with ATSC-compatible receivers.

FEC scheme for encoding two bit-streams

An encoding system is configured to allow data to be transmitted at one of two selectable bit-error-rate quality factors. The first bit-error-rate quality factor selection corresponds to the conventional ATSC FEC encoding systems, and the second bit-error-rate quality factor selection provides an ATSC-like FEC encoding scheme that substantially improves the bit-error-rate. The first quality factor selection effects a &frac23; trellis encoding, whereas the higher quality factor selection effects a &frac13; trellis encoding. Because the high-quality trellis encoding rate of &frac13; is half the lower-quality trellis encoding rate of &frac23;, the data rate of this high-quality encoded bit-stream is half that of the conventional lower-quality encoded bit-stream. The &frac13; trellis encoding is effected using an ATSC-compatible encoding and a modified symbol mapping. The encoding scheme provides 2:1 data redundancy and the symbol mapping provides a maximum distance for the redundant encoding. By combining techniques that each decrease the likelihood of an uncorrectable error at the receiver, the substantial improvement in bit-error-rate can be achieved. At the receiver, a single trellis decoder with different metric tables is used to decode the two bit-streams, thereby providing substantial compatibility with ATSC-compatible receivers.

For use in a receiver capable of decoding trellis encoded signals, there is disclosed an apparatus and method for reducing error propagation in a decision feedback equalizer. The apparatus of the invention comprises a trellis decoder and a decision feedback equalizer coupled to the path memory outputs of the trellis decoder. The decision feedback equalizer is capable of obtaining symbol values from the trellis decoder and using the symbol values as estimates in channel equalization. In one embodiment of the invention, a first equalizer and trellis decoder combination is used to estimate a symbol stream. Then a second equalizer and trellis decoder combination is used to further minimize error by operating on the output of the first equalizer and trellis decoder combination.

System and method for reducing error propagation in a decision feedback equalizer of ATSC VSB receiver

There is disclosed a digital filter cell capable of processing in a first mode a first signal having real data components only and processing in a second mode a second signal having real data components and imaginary data components. The digital filter cell comprises: 1) a plurality of serially coupled coefficient registers for receiving a sequence of coefficients; 2) a plurality of serially coupled data registers for receiving a sequence of digital data samples, each register having a tap output; 3) a data multiplexer having a plurality of input channels for receiving the tap outputs from the plurality of serially coupled data registers; and 4) a product summation circuit having a first input coupled to an output of the data multiplexer and a second input coupled to an output of a selected one of the plurality of serially coupled coefficient registers. The product summation circuit generates a summation of a plurality of products formed by sequentially multiplying each coefficient received from the selected coefficient register by a corresponding digital data sample received from a selected one of the plurality of serially coupled data registers. The product summation circuit adds each of the plurality of products to the summation when the digital filter cell is operating in the first mode. In the second mode, the product summation circuit selectively adds ones of the plurality of products to the summation or selectively subtracts ones of the plurality of products from the summation.

Growing community of inventors

Tarrytown, NY, United States of America

Patrick D Kelliher