Western Digital Corporation

Patrick D Conley

Jin H Hwang

Virgil V Wilkins

Marc E Acosta

Access to a buffer memory is provided by a controller architecture and method employing an arbiter state machine for control of data transfer between multiple external peripheral devices and the dynamic random access memory buffer. Data transfer channels for each peripheral device include a first-in, first-out sub-buffer. Each data transfer channel communicates transfer requests to the arbiter when data is present in the FIFO. When data transfer to or from the FIFO nears an overrun or underrun condition, the data channel issues an urgent request to the arbiter state machine. The arbiter state machine prioritizes data transfer requests for enabling transfer between the buffer memory and data channels. Once a data transfer is in process it continues uninterrupted unless an urgent request is received from another device. In addition, the invention includes a refresh circuit for the dynamic RAM incorporating similar request and urgent request signals provided to the arbiter state machine for resolution.

FIFO control architecture and method for buffer memory access arbitration

The present invention provides an architecture for sampling incoming asynchronous data pulses and providing synchronous output pulses having a constant pulse width. The invention has an input stage comprising a toggling flip-flop receiving the asynchronous pulses on the clock input. The complementary output of the flip-flop is provided to a dual path synchronizer stage followed by a dual path one-shot stage to terminate the synchronized pulse.

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Fullerton, CA, United States of America

Patrick D Conley