Cadence Design Systems, Inc.

Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Softface, Inc.

Cadance Design Systems, Inc.

Patrick Charles McGeer

Alexander Saldanha

Patrick Scaglia

Szu-Tsung Cheng

Luciano Lavagno

Norman Paul Jouppi

Dejan S Milojicic

Alan Hersh Karp

Moray McLaren

Michael Jude Meyer

Vinay Saxena

Mark S Miller

Alberto Sangiovanni-Vincentelli

Alvin Auyoung

Luca Carloni

Thomas Eaton Conklin

A system receives a request to filter access by a client device to content over a network and causes access to network content by said client device to be filtered.

Filtering access to network content

Continuous recording multichannel disk-based data logging apparatus. The apparatus includes a plurality of disk drives and an interface including a plurality of parallel inputs. The interface is responsive to data at the inputs to write the data on an active plurality of the disk drives, at least one disk drive being idle. The interface is responsive to a user request for data on one of the active disk drives to substitute an idle disk drive into the active plurality in place of that one, to read the requested data, and to cause that one to become idle.

Continuous recording multichannel disk-based data logging

A collection of job slots correspond to placement of observed jobs associated with a plurality of job categories in a data processing environment. An incoming job is received, and based on a job category of the incoming job, the incoming job is assigned to a particular one of the job slots to perform placement of the incoming job on physical resources.

Job placement based on modeling of job slots

A method for authentication in a client computer and a remote computer is disclosed. A client base value is obtained, selected by a user of the client computer for at least a first usage purpose. A client integer is obtained, selected by the user for at least a second usage purpose. The client base value is combined with the client integer to obtain a client combination. The client combination is hashed to obtain a client password.

Authentication

A system and method are provided for selectively inferring latch elements in a circuit design from an event-driven hardware description language (HDL) file to an event-independent format. The method includes modeling the file as a plurality of data flow equations, analyzing the plurality of equations for uninitialized variables, and placing a latch at any utilized, uninitialized variable. Control signal information for an inferred latch is also derived during the data flow analysis.

Latch inference using dataflow analysis

A method and system for converting plain text into structured data. Parse trees for the plain text are generated based on the grammar of a natural language, the parse trees are mapped on to instance trees generated based on an application-specific model. The best map is chosen, and the instance tree is passing to an application for execution. The method and system can be used both for populating a database and/or for retrieving data from a database based on a query.

Creation of structured data from plain text

A hardware design language V&plus;&plus; is described. V&plus;&plus; provides an automatically designed and implemented communications protocol, embedded by a compiler in the design itself. This protocol permits transparent, automatic communication between modules in a hardware design. The protocol generalizes current design practice and impacts neither the cycle time, nor the area, of a typical system. Incorporating this protocol in the language itself frees the designer from the task of writing communications code, and ensures that two communicating modules follow the same low-level protocol. In V&plus;&plus; each program is directly interpreted as a network of communicating finite state machines. The composition of two V&plus;&plus; programs is a V&plus;&plus; program, with well-defined, deterministic semantics.

Hardware design language for the design of integrated circuits

A system and method increases discrete function simulator performance by creating a data structure that completely and accurately models a system of discrete function elements. A discrete function simulator simulates the system using the data structure. Sequential circuits are converted into blocks of combinational elements having latch variables stored to and read from memory. The simulator performance is dependent upon the number of system inputs and outputs and not on the number of discrete function elements in the circuit being simulated.

System and method for simulating discrete functions using ordered

A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method includes the steps of determining a set of gates in the circuit coupled to the first primary input lead, the set of gates coupled to a set of edges, determining the 1-controllability of each edge in the set of edges; providing a binary OR tree to the circuit; coupling the set of edges to the binary OR tree; providing an AND gate to the circuit; coupling the AND gate to the binary OR tree and to the first primary input lead; providing a binary AND tree to the circuit; uncoupling the first primary input leads from the set of gates; and coupling the binary AND tree to the AND gate, to the binary OR tree, and to the set of gates.

Conditional selection method for reducing power consumption in a circuit

A method for generating a low-power circuit from a Shannon graph having a plurality of primary inputs, a plurality of nodes including parent and child nodes, a first end-terminal, and a second end-terminal, each of the plurality of nodes having output edges associated therewith, includes the steps of: substituting the plurality of nodes and associated output edges with a plurality of cells, one cell for each node and output edge associated therewith, each cell including a plurality of elements; coupling a cell substituted for a parent node to cells substituted for child nodes of the parent node; and bypassing particular elements of child nodes having only one parent node.

Method for reducing power consumption of switching nodes in a circuit

A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, includes the steps of: determining a dominator edge and dominated gates in the circuit, the dominated gates coupled to the first primary input lead and to edges of the plurality of edges dominated by the dominator edge; providing a dominator selector circuit to the circuit; coupling the dominator selector circuit to the dominator edge and to the first primary input lead; uncoupling the dominated gates from the first primary input lead; and coupling the dominated gates to the dominator selector circuit.

Growing community of inventors

Orinda, CA, United States of America

Patrick Charles McGeer