Analog Devices,inc.

Analog Devices International Unlimited Company

Other

Analog Devices Global

Analog Devices Global Unlimited Company

Patrick C Kirby

Colin Gerard Lyden

Dennis A Dempsey

Tudor M Vinereanu

Dermot G O'Keeffe

Donal P Geraghty

Donal Bourke

Aidan J Cahalane

Gavin Patrick Cosgrave

Roderick McLachlan

Denis Martin O'Connor

Albert C O'Grady

Donal G O'Sullivan

Sharad Vijaykumar

Michal Brychta

Colm F Slattery

Valerie Hamilton

Patrick F M Poucher

Catherine J Redmond

Christopher A Kenny

Derrick Hartmann

Bride Ni Riagain

Michael Collins

Denis O'CONNOR

Albert O'GRADY

Colm Slattery

Dermot O'Keeffe

A line protector circuit comprises an external side switch circuit coupled to an external circuit node of the line protector circuit, an internal side switch circuit coupled in series to the external side switch circuit and an internal circuit node of the line protector circuit, a high supply circuit node and a low supply circuit node, and switch control circuitry configured to deactivate the internal side switch circuit and divert a bias current from the external side switch to the low supply circuit node when the external voltage exceeds a high supply voltage of the high supply circuit node.

Bootstrapped line-protector CMOS switch

Systems for monitoring or control can include reconfigurable input and output channels. Such reconfigurable channels can include as few as a single terminal and a ground pin, or such channels can include three or four terminal configuration such as for use in four-terminal resistance measurements. Channel reconfiguration can be accomplished such as using software-enabled or firmware-enabled control of channel hardware. Such channel hardware can include analog-to-digital and digital-to-analog conversion capability, including use of a digital-to-analog converter to provide field power or biasing. In an example, compensation can be provided to suppress a leakage current from flowing through a digital output to a load connected to the reconfigurable channel terminal, particularly when the digital output is disabled.

Leakage reduction for multi-function configurable circuit

A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N&#x2212;1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2&#x3c0; radians or a multiple thereof, where N is greater than 1.

Control circuit for use with a four terminal sensor, and measurement system including such a control circuit

Systems for monitoring or control can include reconfigurable input and output channels. Such reconfigurable channels can include as few as a single terminal and a ground pin, or such channels can include three or four terminal configuration such as for use in four-terminal resistance measurements. Channel reconfiguration can be accomplished such as using software-enabled or firmware-enabled control of channel hardware. Such channel hardware can include analog-to-digital and digital-to-analog conversion capability, including use of a digital-to-analog converter to provide field power or biasing. In an example, the interface circuit can provide a selectable impedance.

Configurable hardware platform for measurement or control

The invention provides a multi-channel DAC circuit which provides for correlation between selected ones of the multiple channels such that a single set of calibration coefficients may be used for calibration of multiple channels.

Digital to analog converter with shared calibration

A DAC architecture is described. The architecture is specifically adapted to provided an analog voltage output based on a digital input word. The architecture includes a resistor ladder configuration sub-divisible into a first component, adapted to convert a lower part of the input word, and a second component adapted to convert an upper part of the input word. The DAC is calibrated such that the first component can be used to tune the output of the second component on selection of specific segment from the second component.

Digital-to-analog converter structures

A circuit () comprising eight DACs (to), the analog outputs of which are applied to the non-inverting inputs () of corresponding op-amps (to) for gaining up the analog output voltage from the corresponding DAC (). The op-amps () are identical, and are configured in a non-inverting mode with a closed loop gain of two provided by first and second resistors (R) and (R). Primary outputs () of the op-amps () are coupled to output pins (to) of the circuit (). The second resistors (R) couple primary inverting inputs () of the op-amps () to a common lo voltage reference rail (), which is coupled to a true ground reference pin () through a coupling wire ()which exhibit a combined inherent resistance (R). The voltage reference on the common voltage reference rail () varies with time as the output signals of the pa-amps () vary, and would thus result in cross-talk between the DACs (to). Each op-amp () comprises a secondary differential input amplifier stage (), the non-inverting and inverting inputs () of which are coupled to the common voltage reference rail () and the ground reference pin (), respectively. The secondary differential input stage () provides a secondary current to a node () in the op-amp () in response to variation in the time varying voltage reference for summing with an intermediate current provided through the node () by a primary differential input amplifier stage () of the op-amp () for correcting the output voltage signal on the primary output () for variation in the voltage reference on the common voltage reference rail ().

OP-AMP CONFIGURABLE IN A NON-INVERTING MODE WITH A CLOSED LOOP GAIN GREATER THAN ONE WITH OUTPUT VOLTAGE CORRECTION FOR A TIME VARYING VOLTAGE REFERENCE OF THE OP-AMP, AND A METHOD FOR CORRECTING THE OUTPUT VOLTAGE OF SUCH AN OP-AMP FOR A TIME VARYING VOLTAGE REFERENCE

A multi-channel DAC having a digital input port ( ) for receiving digital input codes and a plurality of analogue output terminals (OUT to OUTN) on channels (CH to CHN) on which corresponding analogue signals are outputted, comprises a primary DAC ( ) which receives the digital input codes from the input port ( ). Analogue signals from the primary DAC ( ) are selectively and sequentially sampled onto infinite sample and hold circuits (SH to SHN) of the channel (CH to CHN) through primary switches PS to PSN) under the control of a primary control circuit ( ). Each infinite sample and hold circuit (SH to SHN) comprises a secondary DAC ( ) which outputs an analogue signal which closely approximates to the sampled analogue signal from the primary DAC ( ) and which is held on the corresponding output terminal (OUT to OUTN). Secondary digital codes may be selectively applied to the secondary DACs of the respective infinite sample and hold circuits SH to SHN for incrementing or decrementing the analogue signal held on the corresponding output (OUT to OUTN).

Digital to analog converting circuit

An infinite sample-and-hold circuit which employs a DAC and an ADC coupled with a mode control circuit. In acquisition mode, the mode control circuit connects the analog input signal to the ADC. The ADC drives the DAC and when the DAC output equals the analog input, the mode control circuit disconnects the analog input and the DAC drives the output in hold mode. The mode control circuit preferably includes a comparator/buffer circuit including switching circuitry. The ADC is preferably of the successive approximation type. The comparator/buffer is used in two modes: (1) open loop, as a comparator, and (2) closed loop, as a buffer. During acquisition, the comparator mode is used, while in hold mode the buffer mode is used. The utilization of the same amplifier to provide both functions allows cancellation of offset errors otherwise introduced by the comparator and buffer, at least to a first order.

Infinite sample-and-hold circuit

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Limerick, Ireland

Patrick C Kirby