Harris Corporation

Intersil Corporation

Intersil Americas Inc.

Other

Patrick Anthony Begley

Anthony L Rivoli

William R Young

Donald Frank Hemmenway

Jeanne Marie McNamara

George S Bajor

Dustin Alexander Woodbury

Michael Sean Carmody

Stephen J Gaul

Matthew M Salatino

Jose Avelino Delgado

Stuart Pullen

Arecio A Hernandez

Jeffrey M Strang

David W Hoyt

John T Gasner

Rex Everett Lowther

Donald R Preslar

Lawrence G Pearce

Stuart W Pullen

John J Hackenberg

David George Hoyt

Nicolaas V Vonno

Choong S Rhee

Gyorgy Bajor

Pulse width modulated (&ldquo;Class D&rdquo;) amplifiers and controllers switching in the 50 khz to 2 MHz range generate harmonics that interfere with AM radio reception. This interference has precluded wide spread acceptance of class D amplifiers in products that include an AM radio. The amplifier described here uses a a harmonic avoidance modulator when operating with an AM radio to avoid generating harmonics at the receiver selected frequency or the intermediate (IF) frequency thereof.

Dual mode class D amplifiers

Pulse width modulated (&ldquo;Class D&rdquo;) amplifiers and controllers switching in the 50 khz to 2 MHz range generate harmonics which interfere with AM radio reception. This has precluded wide spread acceptance of class D amplifiers in products with an AM radio. The amplifiers described here use a modified modulation technique when operating with an AM radio to avoid generating harmonics at the receiver selected frequency or its intermediate (IF) frequency. One embodiment uses a harmonic avoidance modulator. A second embodiment uses two or more oscillators and tests for the least distorted output signal. A third embodiment switches the mode of operation to a class AB amplifier when an AM signal is amplified.

A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches . Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

Wafer trench article and process

Integrated circuit air bridge structures and methods of fabricating same

A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

Conductive elements which provide interconnections (air bridges between circuits) and components such as capacitors and inductors may be incorporated in the devices in a manner to reduce parasitic effects in the operation of the devices while providing close spacing which enhances the performance of the devices at high frequency. Separate substrates are provided respectively having the integrated circuits formed therein and covering, preferably sealing the integrated circuits. The air bridge conductive components (interconnections, capacitors or inductors) are formed separately in the covering substrate which is assembled with the substrate having the integrated circuit as a lid which seals and packages the circuits and the conductive element or component contained in the lid. The conductive component may be separated by cavities formed in the lid substrate or in the substrate having the integrated circuit device already formed therein. Assembly may take place at temperatures lower than necessary for fusion bonding and diffusion commonly used in the fabrication of integrated circuits. Bonds which are used may be metal, oxide or plastic (polymer) bonding material.

A class D amplifier 100 has an integrator 10, a comparator 12, and a frequency compensation and gain control (FCGC) circuit 40. The FCGC circuit 40 senses the output and reduces the gain in order to keep the sampling frequency high enough to avoid audio artifacts.

Variable frequency class D modulator with built in soft clipping and

A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

Process of forming trench isolation device

A wafer level hermetically packaged integrated circuit has a protective cover wafer bonded to a semiconductor device substrate wafer. The substrate wafer may contain a cavity. The cover wafer seals integrated circuits and other devices including but not limited to air bridge structures, resonant beams, surface acoustic wave (SAW) devices, trimmable resistors, and micromachines. Some devices, such as SAWs, are formed on the surface of cavities formed in the protective cover wafer. Die are separated to complete the process.

Lid wafer bond packaging and micromachining

A bonded wafer 10 has a silicon device layer 20 bonded to a layer of semi-insulating material 14, preferably a mobility degraded silicon such as polycrystaline silicon. Layer 14 is thick enough and substrate 16 is conductive enough to reduce resistive losses when devices in layer 20 are operated at frequencies above 0.1 Ghz. Substrate 16 is conductive enough and semi-insulating material 14 is resistive enough to prevent cross-talk among devices in layer 20.

Semi-insulating wafer

An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.

Programmable element in barrier metal device

A focal plane array and an associated technique for manufacturing such an array, employ a first, substantially planar semiconductor substrate, that contains a densely compacted array of photodiodes, interconnected with a plurality of second semiconductor substrates in which the signal processing electronics for the array are formed. The backside of the focal plane array-containing substrate has an associated array of conductive bumps to which the respective photodiodes on the imaging side are electrically connected. Within plural ones of second semiconductor substrates, each of which is associated with a respective row of the array of photodiodes there are integrated the signal processing electronics for that row. Formed along side edge portions of the second substrates are a plurality of metallic bumps which are conductively connected to the signal processing electronics. Each signal processing substrate is conductively joined to the photodiode chip by corresponding bumps that have been electroplated along the side edge portion of that second semiconductor substrate to internal conductive regions that terminate at that side edge portion. Each conductive region is preferably comprised of doped semiconductor material which extends to the side edge portion of the substrate and is connected to regions of the signal processing devices within the semiconductor substrate.

Growing community of inventors

West Melbourne, FL, United States of America

Patrick Anthony Begley