USA As Represented by Secretary of the Navy

Patrick A Shoemaker

Randy L Shimabukuro

Gene L Haviland

Graham A Garcia

Isaac Lagnado

Alfons Tuszynski

Michael E Stewart

James R Feeley

A non-volatile, bidirectional electrically programmable integrated memory ement is describe which includes a dielectric structure supported by a substrate and a programming terminal supported by the dielectric structure. The programming terminal includes: (1) a first polysilicon structure; a second polysilicon structure; and an electrically conductive first interconnect which electrically connects the first polysilicon structure to the second polysilicon structure; (2) a floating gate structure supported by the dielectric structure which includes: (a) a third polysilicon structure which overlies and is separated from a section of the first polysilicon structure by the dielectric structure; (b) a fourth polysilicon structure which is overlain and separated from a section of the second polysilicon structure by the dielectric structure; and (c) an electrically conductive second interconnect which electrically couples the third polysilicon structure to the fourth polysilicon structure. The memory element also includes a capacitor electrically connected to the second interconnect.

Non-volatile, bidirectional, electrically programmable integrated memory

An integrated circuit memory element is capable of storing analog information. The memory value can be increased and decreased incrementally with no knowledge of the current state and may be stored for a long period of time. Analog memory information is stored as an electrical charge on a floating gate structure and modification of this information is accomplished by the use of hot-carrier injection to transport electrons off of as well as onto the floating gate (to erase as well as to program electrically). Charge is written onto and off of the gate by injection capacitors in deep depletion and is accomplished by having the floating gate contiguous with a piece of crystalline p-type silicon, in which a deep-depletion region may be formed so that hot electrons may be ejected from (ejected off of) the floating gate structure through the surrounding insulating oxide, and having the floating gate structure capacitively coupled to a second piece of crystalline silicon from which electrons may be injected onto the floating gate structure. The novelty of the invention resides in the utilization of avalanche injection of electrons onto and off of the floating gate using injection capacitors. This requires far less current and is more symmetric than the original dual polarity MOS analog memory devices of the prior art.

MOS analog memory with injection capacitors

The present invention provides a circuit for eliminating quadratic and offset errors in the output of a CMOS four-quadrant analog multiplier. These errors are eliminated by feedback circuits that each include one or more CMOS four-quadrant analog multipliers.

Circuitry for compensating for transistor parameter mismatches in a CMOS

A non-volatile analog memory circuit includes charge depositing and storing ircuitry, voltage sensing circuitry, and closed-loop control circuitry. The charge depositing and storing circuitry includes a floating gate operable to receive charge deposited on it. The voltage sensing circuitry supplies an analog output in response to the sensed gate potential. The closed-loop control circuitry is used to control charge deposition. The control circuitry is operable to change the charge on the gate by directing electrical pulses of appropriate polarity to the charge depositing and storing circuitry. This is done to diminish the error between the analog output signal of the charge sensing circuitry and an analog input signal for providing a substantially accurate representation of the analog input signal.

Non-volatile analog memory circuit with closed-loop control

The present invention provides a linear resistance element comprising a p of transistors. The transistor pair includes first and second depletion-type field effect transistors each having a gate, a source electrode, a drain electrode, a channel mobility, and a threshold voltage. The source and drain electrodes of each transistor define a source-drain current path through a channel. The first and second transistors are connected with their source-drain paths in series with each other. The gates of the first and second transistors are connected in common to the series connection between the source-drain current paths. The channel width-to-length ratio, channel mobility, and threshold voltage of the first transistor are substantially equal to the corresponding properties of the second transistor. Any number of transistor pairs may be serially connected together.

Resistive element using depletion-mode MOSFET's

A four-quadrant analog multiplier circuit provides an output which is protional to two voltage inputs that each represent a multiplicand. In a first embodiment, the circuit comprises a complementary pair of field effect transistors having gain constants equal in magnitude and in which the p-channel threshold voltage is larger than the n- channel threshold voltage. The gates of the transistors are coupled in common. One input is added to a bias voltage and the voltage sum is applied to the common gates. The other input and its inverse are separately applied to source/drain terminals of the two transistors, while the remaining source/drain terminals are coupled in common to provide an output node. A second embodiment of the invention is composed of two circuits as described above, where the polarities of the inputs to one pair of transistors are reversed relative to those of the second pair, and the output nodes of the individual pairs are coupled together.

CMOS analog four-quadrant multiplier

A four-quadrant analog multiplier circuit provides an output which is proportional to two voltage inputs. The circuit includes a pair of depletion mode transistors having gain constants equal in magnitude and threshold voltages equal in magnitude. The gates of the transistors are coupled in common. One input is applied to the common gates. The other input and its inverse are separately applied to source/drain terminals of the two transistors.

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Lemon Grove, CA, United States of America

Patrick A Shoemaker