Cirrus Logic Inc.

Compaq Computer Corporation, Inc.

S3 Incorporated, Inc.

Patrick A Harkin

Michael K Larson

Stuart Hecht

Daniel P Wilde

Gautam P Vaswani

Abdel H Suboh

Mark A Lobodzinski

Ronald Anthony Shipp

A graphics processor capable of rendering three-dimensional polygons with color, shading; and other visual effects also corrects interpolation errors that occur as a result of mapping the polygon to a pixel grid display. The processor renders polygons using an Incremental Line-Drawing algorithm and features an error correction circuit capable of adjusting the initial and incremental gradient parameters for each pixel characteristic and then rendering each scan line with the proper orthogonal adjustment. The error correction circuit includes an ortho correction engine for correcting errors in the initial and incremental pixel parameters and an ortho adjust engine to accommodate overflows in the x-coordinate calculations. The processor is able to render the polygons with monotonic gradients in color, shading, depth, and other visual characteristics without interpolation error.

Error correction in a graphics processor

A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes an arbitration logic device enables the graphics processor to temporarily arbitrate shared resources to dissimilar graphics drawing engines. The arbitration logic allows data from the dissimilar drawing engines to be prioritized, depending on the configuration of the underlying computer system, for accessing shared resources.

Arbitration for shared graphics processing resources

A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes a command address feed logic device decodes the display list to determine the register locations in a register file to fill with data. The command address feed logic device decodes the display list and orders a group of registers in the register file in order to perform a sequential write to the register file. By sequentially ordering the register file locations, the command address feed logic device is able to write null or zero data values to the register locations which are not needed to render a primitive, while maintaining a single write cycle to the register file.

Method and apparatus for automatically controlling the destination of a

A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes an XY address for rendering the graphics primitives. A graphics processor, which includes a bypass logic circuit, enables the graphics processor to temporarily store display list commands in an internal storage device while previously fetched display list data is being processed. The bypass logic circuit allows the graphics processor to bypass the internal storage device and write fetched command directly to an execution unit in the graphics processor. By having the bypass capabilities, the graphics processor is able to optimize the internal storing of commands in the display list in the internal storage unit.

Optimized FIFO memory

An apparatus and method are disclosed for buffering graphics commands in a video graphics system, and for implementing graphics macro commands. The invention makes use of off-screen portions of video memory to create a dynamic command FIFO for commands, and to store command sequences for later or repeated use ('macros'). A command FIFO controller is provided, along with an on-chip bus FIFO and an on-chip command buffer (which is also a FIFO). Several multiplexers are also provided, so as to enable the command FIFO controller to create several different paths for commands coming into the graphics controller. Incoming commands may be routed to the command execution circuitry in several different ways: through the bus FIFO and command buffer to the command execution circuitry, directly to the command execution circuitry by bypassing the bus FIFO and command buffer, or from the bus FIFO into video memory to be stored in a dynamic command FIFO and later retrieved and sent into the command buffer. The command FIFO controller is also provided with macro address generation logic for providing read pointers to macros stored in video memory, read and write address generation logic for accessing the dynamic command FIFO stored in video memory, status generation logic for use in controlling the dynamic command FIFO, and busy status logic for use in software synchronization

Graphics controller utilizing video memory to provide macro command

A graphics system includes a graphics controller for rendering polygons with a minimum number of steps and registers. A host processor generates a display list that includes only the values necessary for rendering a primitive. The graphics controller includes a register file for receiving the display list either directly from the host processor or from system memory in which the host processor stored the display list. The graphics controller also includes logic to decode operational codes to ascertain which values from the register file must be used for rendering a primitive and which values can be skipped. Only the necessary values are transmitted to polygon and texture engines also included within the graphics processor.

Register set reordering for a graphics processor based upon the type of

A display controller includes a text engine which stores font information, including image and width information, in a unused portion of the frame buffer. A character string comprising width vectors and indices which point to the characters to be drawn, is passed to the display controller from the driver software. Once the character string is received, the text engine draws the indicated characters by reference to the font information previously stored in the character information memory by the driver, allowing the operating system to continue operations while the text string is being drawn to the viewport of the frame buffer.

Display controller with accelerated drawing of text strings

A video controller has one or more shared pins coupled to respective configuration signals. The shared pins are also coupled to other devices external to the video controller. Responsive to a reset signal, the configuration signals are stored in a configuration register. At other times, the external devices can overcome the configuration signals such that the shared pins may be used for other operations of the video subsystem.

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Austin, TX, United States of America

Patrick A Harkin