Hewlett-Packard Development Company, L.p.

Tandem Computers Incorporated

Patricia L Whiteside

William P Bunton

John C Krause

John Michael Brown

Scott Stuart Smith

Robert W Horst

David J Garcia

John D Coddington

William J Watson

David P Sonnier

William F Bruckert

Douglas E Jewett

William Edward Baker

Richard W Cutts, Jr

Susan S Meredith

Steven C Meyers

Geoffrey I Iswandhi

Stephen G Low

Daniel L Fowler

Frank A Williams

Linda Ellen Zalzala

Randall G Banton

Paul N Hintikka

James Stevens Klecka

Curtis Willard Jones, Jr

Gary F Campbell

Barry Lee Drexler

Harry Frank Elrod

An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one 'symbol group' at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from the buffers having start symbols is temporarily suspended.

High-speed interconnection adapter having automated lane de-skew

A multi-lane link that automatically detects if the lanes in the link have been reordered and corrects the order of the lanes. In one embodiment, the link includes a transmitter and a receiver. The receiver is configured to receive a plurality of lanes and includes a receiver logic circuit configured to receive signals from each of the plurality of lanes. Lane misordering is corrected during a training sequence in which a first training sequence and a second training sequence are bilaterally transmitted between the transmitter and receiver. The receiver monitors the training sequence for symbols that are unique to each lane and if an unexpected symbol is detected in the lane, the receiver logic circuit will correct the order of the lanes. The link further comprises a transmitter logic circuit configured to transmit signals to the lanes. The transmitter logic circuit is configured to reorder the sequence of the signals transmitted to the lanes if the transmitter does not detect a response from the receiver. The transmitter logic circuit may consist of a bank of multiplexers configured to transmit a selected one of two input signals to be transmitted through a lane. Similarly, the receiver logic circuit may comprises a bank of multiplexers configured to transmit a selected one of two input signals received from a lane. The unique lane identifiers symbols are preferably insensitive to binary inversion and are preferably 10-bit symbols compatible with an 8B/10B encoding scheme.

High-speed interconnection link having automated lane reordering

An adapter configured to automatically detect and compensate for differential signal inversion is herein disclosed. In one embodiment, the adapter is part of a computer network having differential conductor pairs conveying differential signals between network devices. The network devices include adapters coupled to transmit and receive signals via the differential conductor pairs. The adapter preferably includes a lane receiver, a decoder, and a synchronization circuit. The lane receiver is configured to receive a single differential signal and to convert the differential signal into a sequence of code symbols. The decoder decodes the code symbols to produce a sequence of received symbols. The synchronization circuit examines the sequence of received symbols to determine if it is incorrect due to inversion of the differential signal, and if so, it causes the lane receiver to correct for the differential signal inversion. It is expected that the received symbol sequence will include a training symbol sequence which will have a start symbol whose decoded value is unaffected by differential signal inversion, and a training symbol whose decoded value is indicative of the presence or absence of invasion. The synchronization circuit, upon identifying the training sequence, will thus be able to determine whether inversion exists and be able to automatically correct for it.

High-speed interconnection adapter having automated crossed differential pair correction

An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device Initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one &ldquo;symbol groups&rdquo; at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from buffers having start symbols is temporarily suspended.

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-fast, fail-functional, fault-tolerant multiprocessor system

A computer system with a number of subsystems or modules on separate circuit boards employs electronic keying to ensure proper configuration of these boards. A power key arrangement associated with a plug-in connector enables a separate power supply for each set of boards. A power supply turn-on signal is routed through a uniquely-configured connector path for each board, so the power supply turn-on is inhibited for improper configurations. The uniquely-configured connector path may use either a series or a parallel implementation. The series implementation employs a set of diodes connected for conduction in either of two directions, with the mating connector having its conductor paths connected to match the diode configuration; in this manner, the power supply enable signal can only flow through the series path if the proper board is plugged into a properly-coded slot, in which case the power supply to activate this board is activated through the series path including the diodes. The parallel implementation employs a given number of connector pins to establish the coding for each board, and each pin is either open-circuited or connected to ground; if this coding of the subsystem board is not the same as that of the slot into which it is plugged then the power supply activation signal will be shorted to ground by one or the other of the coded pins.

Module for insertion into a multi-module system having electronic keying

Multi-board system having electronic keying and preventing power to

Growing community of inventors

Austin, TX, United States of America

Patricia L Whiteside