Samsung Electronics Co., Ltd.

Patricia Kay Sturm

Jack C Wybenga

Patrick W Ireland

Pradeep Dinkar Samudra

Steven Eugene Tharp

Mark Lang

Jorge Fossati

Yingwei Wang

Gary Russell Chesnut

Youngil Kim

A router for interconnecting external devices coupled to the router. The router comprises: 1) a switch fabric; and 2) a plurality of routing nodes coupled to the switch fabric, wherein each of the plurality of routing nodes comprises packet processing circuitry for transmitting data packets to, and receiving data packets from, the external devices and for transmitting data packets to, and receiving data packets from, other ones of the plurality of routing nodes via the switch fabric. The packet processing circuitry comprises: i) a first network processor comprising a first plurality of microengines, each of the first plurality of microengines capable of performing security and classification functions associated with the data packets; and ii) a second network processor comprising a second plurality of microengines, each of the second plurality of microengines capable of performing security and classification functions associated with the data packets.

Apparatus and method for performing security and classification in a multiprocessor router

A routing apparatus comprising: 1) a first router coupled to a first plurality of Ethernet links; and 2) a second router coupled to a second plurality of Ethernet links, wherein selected ones of the first plurality of Ethernet links are coupled to selected ones of the second plurality of Ethernet links to thereby form Ethernet trunk groups in which traffic associated with a plurality of Ethernet ports are aggregated into a single logical port. The routing apparatus further comprises a first high-speed link and a second high-speed link directly coupling the first router and the second router and forming a self-healing ring for transferring data packets between the first and second routers. In response to a failure associated with the failing one of the first and second routers, the first and second high-speed links transfer data traffic from the failing router to the non-failing router.

Apparatus and method for architecturally redundant ethernet

A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each routing node is capable of transmitting data packets to, and receiving data packets from, the external devices and is further capable of transmitting data packets to, and receiving data packets from, other routing nodes via the switch fabric. The router also comprises a control processor for comparing the N most significant bits of a first subnet address associated with a first external port of a first routing node with the N most significant bits of a second subnet address associated with a second external port of the first routing node. The router determines a P-bit prefix of similar leading bits in the first and second subnet addresses and transmits the P-bit prefix to other routing nodes.

Apparatus and method for route summarization and distribution in a massively parallel router

A router for transferring data packets between external devices. The router comprises: 1) a switch fabric; and 2) R routing nodes coupled to the switch fabric. Each routing node exchanges data packets with the external devices and with other routing nodes via the switch fabric. A first routing node comprises: i) an inbound network processor comprising a first plurality of microengines capable of forwarding incoming data packets from external ports to the switch fabric; ii) an outbound network processor comprising a second plurality of microengines capable of forwarding outgoing data packets from the switch fabric to the external ports; and iii) an asynchronous variables circuit for controlling access of the inbound and outbound network processors to at least one of i) a shared resource and ii) a shared variable in the router.

Apparatus and method for sharing variables and resources in a multiprocessor routing node

A lookup circuit for translating received addresses into destination addresses. The lookup circuit comprises M pipelined memory circuits for storing a trie table for translating a first received address into a first destination address. The M memory circuits are pipelined such that a first portion of the first received address accesses an address table in a first memory circuit. An output of the first memory circuit comprises a first address pointer that indexes a start of an address table in a second memory circuit. The first address pointer and a second portion of the first received address access a particular entry in the address table in the second memory circuit. An output of the second memory circuit comprises a second address pointer that indexes a start of an address table in the third memory circuit, and so forth.

Apparatus and method for performing high-speed lookups in a routing table

An apparatus and method for using an error correcting code to achieve data compression in a data communication network is disclosed. Data compression is achieved by performing an error correction encoding operation on input data. Data compression is further achieved by providing, for transmission across a communication channel, compressed data that is representative of the input data. The compressed data preferably includes error correction information produced by the error correction encoding operation. The compressed data requires less transmission channel capacity than does the input data.

Apparatus and method for using an error correcting code to achieve data compression in a data communication network

A method for switching frames in a switching system is provided. The method includes receiving a first stripe set for a first port at a second port. The first stripe set is stored in a particular location in a queue of the second port. A determination is made regarding whether a first full flag associated with the first port has been set. If the first full flag has not been set, the first full flag is set and the particular location in the queue of the second port is provided to the first port.

Method and system for switching frames in a switching system

A router comprising: i) a switch fabric; and ii) N Layermodules coupled by the switch fabric, each of the N Layermodules capable of receiving data packets in Layerframes and forwarding the received data packets using Layeraddresses associated with the Layerframes, wherein a first one of the Layermodules comprises a Layerrouting engine capable of forwarding a first received data packet through the switch fabric directly to a second one of the Layermodules using a Layeraddress associated with the first received data packet if the first Layermodule does not recognize a Layeraddress associated with the first received data packet.

Router using switching-before-routing packet processing and method of operation

A router for interconnecting external devices coupled to the router. The router comprises: i) a switch fabric; ii) a plurality of routing nodes coupled to the switch fabric, wherein each of the plurality of routing nodes is capable of exchanging data packets with the external devices and with other ones of the plurality of routing nodes via the switch fabric; and iii) a first control processor associated with a first one of the plurality of routing nodes capable of generating a first refined redistribution metric associated with a first route in a routing table of the first routing node. The first control processor generates the first refined redistribution metric based on 1) a first default redistribution metric associated with a first routing protocol associated with the first route and 2) a first routing protocol metric received from the first routing protocol associated with the first route.

Apparatus and method for multi-protocol route redistribution in a massively parallel router

A packet counter/adder for use in a multiprocessor system. The packet counter stores a counter value of data packets processed by a plurality of processors in the multiprocessor system. The packet counter comprises a first register capable of storing the counter value, wherein the counter value in the first register is incremented by a write operation to a first address associated with the first register. The counter value in the first register may be set to a specified value by a write operation to a second address associated with the first register.

Packet counters and packet adders for traffic profiling in a multiprocessor router

A router for transferring data packets between external devices. The router comprises: 1) a switch fabric; and 2) R routing nodes coupled to the switch fabric. Each routing node exchanges data packets with the external devices and with other routing nodes via the switch fabric. A first routing node comprises: i) an inbound network processor having a first plurality of microengines that forward incoming data packets from external ports to the switch fabric; ii) an outbound network processor having a second plurality of microengines that forward outgoing data packets from the switch fabric to the external ports; and iii) a plurality of registers for transferring messages between the first and second plurality of microengines. The registers may be 32-bit mailboxes for transferring short messages or 2 Kbyte FIFO buffers for transferring one or more large data packets.

Apparatus and method for inter-processor communications in a multiprocessor routing node

A router for interconnecting external devices comprising: 1) a switch fabric; and 2) R routing nodes coupled to the switch fabric. Each of the R routing nodes exchanges data packets with the external devices via network interface ports and with other routing nodes via the switch fabric. A first routing node comprises: i) an inbound network processor for receiving incoming data packets from a network interface port; ii) an outbound network processor for transmitting data packets to the network interface port; and iii) a shared memory accessible by the inbound and outbound network processors for storing a current trie tree search table and a current vector table used to index into the trie tree search table. A control plane processor generates an updated vector table to replace the current vector table and notifies the inbound and outbound network processors that the updated vector table is available.

Apparatus and method using vector table indirection to maintain forwarding tables in a router

A routing table search circuit for determining a first destination address for a first received data packet. The routing table search circuit comprises: i) a forwarding table containing destination addresses; and ii) a trie tree search table for translating an address portion of the first received data packet into a destination pointer for accessing the first destination address in the forwarding table. A first stage of the trie tree search table is searched using a received address pointer from a previous stage of the trie tree search table and a first m-bit symbol of the address portion. The routing table search circuit also comprises at least one consecutive symbols table and a control circuit for determining that a second consecutive m-bit symbol is the same as the first m-bit symbol. The control circuit then determines a total number of consecutive identical m-bit symbols beginning with the first m-bit symbol.

Apparatus and method for performing forwarding table searches using consecutive symbols tables

A router for transmitting data packets to and receiving data packets from N interfacing peripheral devices. The router comprises a plurality of processors that exchange data packets with each other over a common bus. A source processor transmits a data packet to a destination processor by storing the data packet in an output queue associated with the source processor and transmits an interrupt message to the destination processor. The destination processor, in response to the interrupt message, reads the data packet from the output queue.

Apparatus and method for workflow-based routing in a distributed architecture router

Channelized I/O is provided for a data processing architecture. An application is executed on a data processor. Program instructions are executed in parallel, and independently of the data processor, to provide a plurality of data communication channels which can communicate with an external site that is physically separate from the data processor.

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McKinney, TX, United States of America

Patricia Kay Sturm