Bull S.a.

Patricia Giacomini

Daniel Carteau

Philippe Schreck

A peripheral mass memory subsystem (PSS.sub.1, PSS.sub.2) of an information processing system including at least one central host (H.sub.1, H.sub.2, H.sub.4, H.sub.4), two control units (UC.sub.1, UC.sub.2) and at least one mass memory (BMD.sub.1, BMD.sub.2, . . . ,) with independent electrical power supplies (ALIM.sub.1, ALIM.sub.2, BAT.sub.1, BAT.sub.2) and each having a plurality of structural (hardware+microsoftware) elements (PR.sub.1 -PR.sub.2, DE.sub.1 -DE.sub.2, CA.sub.1 -CA.sub.2, HA.sub.1 -HA.sub.2, DA.sub.1 -D.sub.2) connected to a first and/or a second parallel-type bus (B.sub.1, B.sub.2). The subsystem is characterized in that it includes a microsoftware architecture (AML) that executes the commands of the host and informs the host of changes in state of the mass memory and is embodied by a plurality of functional microsoftware subassemblies (P, H, D, C, S), each of them specific to each structural element of each control unit and implemented in its hardware structure.

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Bois d'Arcy, France

Patricia Giacomini