Other

France Telecom Etablissement Autonome De Droit Public (centre National

France Telecom

Etat Francais

Telediffusion De France

Societe D'applications Generales D'electricite Et De Mecanique Sagem

Fahrenheit Thermoscope LLC

France T&eacute;l&eacute;com

Etat Francais Represente Par Le Ministre Delegue Des Postes Et

L'etat Francais, Represente Par La Ministre Delegue Des Postes Et

Minister of Post, Telecommunications and Space French State, Center

France Telecom Etablissement Autonome De Droit Public (center National

Orange

Patrice Senn

Benoît Miscopein

Jean Schwoerer

Alan Lelah

Gilbert Martel

Mohamed S Tawfik

Pascal Vivet

Jacky Bouvier

Marc Renaudin

Michel Veillard

Michel Pons

Denis Pradel

Eric Andre

Freddy Balestro

Jean Michel Fournier

Gerard Duvic

Laurent Paris

G&eacute;rard Merckel

Andr&eacute; Adrial

Andre Abrial

Eric Batut

The invention relates to a dual mode radio frequency reception device of the type enabling the reception firstly of multi-carrier broadcast signals in a first frequency band and secondly radio positioning signals in a second frequency band, comprising a single preprocessing module (), particularly including a pass-band antenna filter () in which the pass-band includes at least the said first and second frequency bands, and outputting firstly to a first processing system () to process the said multi-carrier broadcast signals, and secondly to a second processing system () to process the said radio positioning signals.

Dual mode radio frequency reception device and corresponding multimedia receiver

The integrated circuit comprises an inductor made at a metallization level of the circuit and a buried layer situated in the substrate of the integrated circuit under the said inductor, and connection means linking the inductor to the buried layer. The connection means are configured in such a way as to ensure the same potential in terms of dynamic response between the inductor and the buried layer. This equipotential is ensured by a transistor in a follower type arrangement made in the substrate and connected in parallel with the stray capacitances under the inductor.

Integrated circuit device comprising an inductor with high quality coefficient

A micro-electronic component for a portable object is of the type which incorporates digital processing means, and an interface for contact-free electromagnetic coupling with a remote station. The digital processing means can operate according to an operating mode of the request/acknowledgement type, which is substantially insensitive to the propagation time, without a global, regular clock. The component additionally comprises adapter means, which can adapt the signals of the contact-free interface to the signals of the digital processing means and vice versa, in order to permit two-way dialogue with the remote station.

Micro-electronic component, incorporating asynchronous digital processing means and a contact-free electromagnetic coupling interface

The device comprises a first input (E1) and a first output (S1) which are capable respectively of receiving and delivering a plurality of analog signals and corresponding digital signals having different predetermined types of transmission specifications and associated with substantially homothetic predetermined elementary frequency attenuation templates. A second input (E2) and a second output (S2) are also provided, capable respectively of receiving and delivering a plurality of digital signals and corresponding analog signals having different predetermined types of transmission specifications, associated with different, substantially homothetic predetermined elementary frequency attenuation templates, as well as first and second signal conversion means arranged respectively between the first input and output and between the second input and output and including a single digital filter (6) in common, having a single frequency attenuation template which is compatible with all the elementary templates.

Signal processing device using several different filterings, especially

Control protective circuit, in particular of liquid crystal display screen. The protective circuit includes three transistors making possible the transfer of the voltage to output pin, the resetting of middle point and the resetting of the output. Application to the control of liquid crystal display screens.

Protective circuit for a control circuit, in particular of liquid

A circuit for controlling the lines of a display screen and including a t means with a single output is disclosed. The test means includes a single test control line (LCT), a single test output line (LST) and a plurality of sample holders (CEBj) and associated gates (Pj) and switches (Ij). The output voltage of the sample holders is transmitted onto a test output block (ST).

Circuit for controlling the lines of a display screen and including test

Sample and hold circuit for a liquid crystal display screen. The circuit comprises two stages, the first with switched capacitance the second with an amplifier device. Application to the control of liquid crystal display screens.

Sample and hold circuit for a liquid crystal display screen

An analog/digital converter supplying logic words constituted by P high order bits and Q low order bits, comprises: a divider (2), 2.sup.P high weight comparators (5), 2.sup.Q low weight comparators (11), and a selector (14). The high weight comparators have their second inputs (E21) enabled by the clock signal (H) and their first inputs (E11) enabled by the reverse clock signal (H.sup.*). The low weight comparators have their first inputs (E12) enabled by the reverse clock signal (H.sup.*) and their second inputs (E22) enabled by the clock signal (H).

High-speed half-flash type analog/digital converter

A two-port switched capacitor filter network of the type comprising two input terminals (4, 6), two output terminals (8, 10) and at least three integrator circuits (12, 14, 16) connected therebetween, each integrator circuit including two inputs provided with capacitors which are switched under the control of two disjoint clock states, said integrator circuits being interconnected to constitute a sampling filter having a selected amplitude/frequency response. The two-port network includes two other integrator circuits (36, 38) whose respective inputs are fitted with capacitors switched under the control of two disjoint clock states, said other integrator circuit being interconnected with each other and with the first-mentioned integrator circuits in order to linearize the phase/frequency response of said filter.

Two-port switched capacitor filter netowrk with linearized

This filter circuit comprises at least one basic cell (2) arranged as a switched capacitor sampling filter, together with a clock suitable for defining two different states for controlling sampling. According to the main characteristic of the invention, the circuit includes upstream switching means (4) suitable for inverting the polarity of the signal input to the cell during one of the two states, and downstream switching means (6) suitable for inverting the output signal from the cell (2). This makes it possible to transpose the filtering frequency band of the cell (2). The circuit is applicable to manufacturing switched capacitor sampling filters in the form of integrated circuits.

Switched capacitor sampling filter

Circuit for producing analog primary signals of a television signal from its digital luminance and chrominance components comprising in series an interpolating digital filter, a digital dematrixer and three digital - analog converters. The interpolating digital filter carried out an oversampling of the luminance signal Y in a ratio of 2 and an oversampling of each chrominance signal CR, CB in a sampling ratio such that the sampling frequency of the luminance and chrominance digital signals has the same sampling frequency. The digital dematrixer produces the primary digital color signals from the oversampled luminance and chrominance components.

Circuit for producing analog signals of primary colors of a television

The invention relates to a double integration or dual slope delta-sigma coder. This coder comprises a first adder receiving on an input (36) a signal E(p) to be encoded and on an input (37) the coded signal S(p), a first integrator receiving on an input (32) an output signal of the first adder, a second adder receiving on an input (38) the output signal (31) of the first integrator, an input (39) of the second adder receiving a signal proportional to the coded signal, a second integrator connected to the second adder, a quantizer circuit (43), whereof one input (D) is connected to an output (41) of the second integrator, an output Q of said quantizer circuit supplying the coded signal S(p), wherein the integrators and adders are constituted by circuits comprising operational amplifiers (30, 40) and switched capacitor arrangements (35, 36, 45, 46).

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Grenoble, France

Patrice Senn