Cp8 Technologies

Gemalto Sa

Trusted Logic

Patrice Hameau

Nicolas Fougeroux

Olivier Landier

Benoît Bole

Renaud Marlet

Nicolas Giraud

Xavier Leroy

Nicolas Regnault

Abraham Brolh

The method for protecting a logic or mathematical operator of the NOR operator type, able to be used for executing a program in a microprocessor electronic module wherein the execution of the NOR operator is replaced by the execution (CAL-XORSEC(1) of a sequence Si operations having for final result a result identical to that of the XOR function. The sequence of operations Si composed of elementary operations with AND, OR and NOT is selected at each XOR operator from a set of eight equivalent sequences (S1 to S8) after determination CAL-NDO) of an order number ND0=1 according to the parameters of the program and/or a random parameter R supplied by a pseudo-random number generator (14).

Method for protecting a logic or mathematical operator installed in an electronic module with a microprocessor as well as the associated embedded electronic module and the system

The inventive method for controlling access to data which is used by reference in a program execution system (including processes and aims) during the program execution consists in memorising by the system the totality of references obtainable by said program with the aid of means considered legal, before any operation which can be prohibited if it relates to values which are not legal references, in verifying by the system whether said values are amongst the legal references memorized for the program and in accepting or rejecting the operation, respectively.

Control of data access by dynamically verifying legal references

A method for secure loading of a key dedicated to securing a predetermined operation into memory of a microchip of an embedded system includes, as a first step, authenticating a security device by generating a first random number using the microchip, transmitting the first random number to the security device, generating a second random number in the security device, generating a first cryptogram from the first and second random numbers by applying an asymmetric signature algorithm using an asymmetric secret key, transmitting at least the first cryptogram to the microchip, and authenticating the security device by verifying the first cryptogram using the public key. A second step includes authenticating the microchip by generating, in the microchip, a secret session key from the first random number by applying a symmetric encryption algorithm using the secret key, generating a second cryptogram by applying a symmetric encryption algorithm using the secret session key, transmitting the second cryptogram to the security device, and authenticating the microchip by verifying the second cryptogram using the session key. A third step includes transferring a dedicated key, encrypted by the session key, into the storage means of the microchip.

Method for making secure the pre-initialising phase of a silicon chip integrated system, in particular a smart card and integrated system therefor

The invention concerns a method for secure storage of a piece of so-called sensitive data, for example an encryption key, in a memory (M) of an embedded microchip system, particularly a smart card (CP). The memory (M) comprises two physically distinct storage devices (), for example a permanent memory of the 'ROM' type (), and a second, re-programmable memory of the 'EEPROM' type (). The piece of sensitive data is divided into at least two parts (d, d'), in a given logical configuration, each of these parts being stored in one of the distinct storage devices (). An additional piece of verification data, a checksum or hash data, can also be stored in the first storage device (), at the same time as the first sensitive data part (d). The invention also concerns an embedded microchip system, particularly a smart card (CP).

Method for secure storage of sensitive data in a memory of an embedded microchip system, particularly a smart card, and embedded system implementing the method

This invention concerns an optimised management method for allocating memory space of an onboard system to a data structure and a corresponding onboard system. The object code packets and the data packets being discriminated, and the memory being subdivided into addressable elementary memory blocks, the method consists in allocating (A) to the object code packets a set of elementary memory blocks located in a first memory space (MS) to addresses substantially adjacent and to the data packets another set of elementary memory blocks located in a second memory range (MS). This enables to avoid fragmentation of the memory zone, during successive installations/deinstallations and to implement very easily an optimal defragmentation procedure, adapted to each type of data, code or application data.

Optimised management method for allocating memory workspace of an onboard system and corresponding onboard system

The invention concerns a method for dynamically allocating memory workspace of an onboard system to a data structure identified by an identification number (ID_A) and the corresponding onboard system. The storage area of the onboard system being subdivided into elementary memory blocks (BL), the method is implemented on the basis of an allocation instruction and an erasure instruction. To allocate (A) an elementary memory block, the method consists in assigning an identification number (ID-A) to the block concerned. To erase (E) an elementary storage block, the method consists in assigning an arbitrary value (AAAA) different from any identification number. The system is applicable to onboard systems, such as multi-application microprocessor cards.

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Boulogne Billancourt, France

Patrice Hameau