Micron Technology Incorporated

Pasquale Pistilli

Elio D'Ambrosio

Pietro Piersimoni

Giovanni Naso

Giovanni Santin

Luca De Santis

Pasquale Conenna

A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.

ROM-based controller monitor in a memory device

The various embodiments provide for programming floating-gate, or flash, memory devices by writing a block of data words to a volatile storage media from an external processor and programming the block of words to the nonvolatile flash memory cells from the volatile storage media without the need for further input from the external processor. In this manner, a block of words may be programmed into the flash memory device using a single write command and avoiding the need for a verify operation after programming each word. By utilizing an internal volatile storage media to receive the block of words prior to writing the individual words to the memory array, the external processor is free to perform other tasks while the programming and verification are performed autonomously by the memory device. Using an external power supply facilitates parallel transfer from the internal volatile storage media to the nonvolatile flash memory cells.

Flash memory programming

A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory.

Write state machine architecture for flash memory internal instructions

A multiple partition memory array has a command user interface for each partition, and a logic interface. The logic interface receives signals from each of the command user interfaces to restrict executable commands in the command user interfaces to those commands that will not tax the system given the current status of each of the command user interfaces.

Multiple partition memory command user interface

A system and method for a write state machine for a non-volatile memory. The write state machine has an associated read only memory (ROM) for storing instructions for operation of the non-volatile memory. The ROM is coupled to an input of a write state machine. An instruction needed to perform an algorithm is stored as a micro-instruction in the ROM such that an instruction sequence is changed by only reprogramming the ROM.

A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

Command user interface with programmable decoder

Method for re-encoding a decoder

A memory device includes an array of flash memory cells organized as a plurality of addressable sectors, control circuitry for controlling operations on the array of flash memory cells, and a plurality of sector tagging blocks, with each sector tagging block being associated with one sector of memory cells. Each sector tagging block is adapted to generate a select signal having a first logic level when its associated sector is addressed. The sector tagging blocks are further adapted to generate a common drain signal having a first logic level when any one of the associated sectors is tagged and addressed and to generate the common drain signal having a second logic level when no addressed associated sector is tagged.

Flash memory sector tagging for consecutive sector erase or bank erase

A method for making a memory device includes forming or fabricating on a first substrate a first array of memory cells, a first read only memory, and a first write state machine which receives instructions from the first read only memory for operating the first array of memory cells. The method further includes forming or fabricating on a second substrate, a second array of memory cells, a second read only memory, and a second write state machine which receives instructions from the second read only memory for operating the second array of memory cells.

Method for making a memory device with plural substrates each having a memory array, a read only memory, and a write state machine

Methods and apparatus to facilitate erasure of multiple sectors of a memory device without the need for externally-supplied erase potentials are advantageous for device testing. During a scan of sector addresses, sector tagging blocks of a memory device provide an output signal to a write state machine indicating whether the addressed sector is tagged for erasure. The sector tagging blocks facilitate resetting of tags on a global basis and setting of tags on a single, bank-wide and/or global basis. Once initiated, the erase operation proceeds to erase each tagged sector of the memory device in sequence without the need for externally-supplied erase potentials and without the need for further direction of the tester hardware. The methods are particularly useful for erasing all sectors of a memory device or all sectors of one memory bank of the memory device.

A system and method for a write state machine for non-volatile memory is disclosed. The system includes an array of memory cells and a write state machine for controlling operations on the array of memory cells. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory. The write state machine is adapted to suspend an execution of one of the operations during an action on a block in the non-volatile memory which is not being accessed by the write state machine.

Growing community of inventors

Cappelle dei Marsi, Italy

Pasquale Pistilli