Micron Technology Incorporated

Pasquale Conenna

Luca De Santis

Giovanni Naso

Pasquale Pistilli

A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.

Memory devices with register banks storing actuators that cause operations to be performed on a memory core

Bus controller

A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.

Memory device controller

A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.

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Cittaducale, Italy

Pasquale Conenna