Nokia Corporation

Nokia Technologies Oy

Pasi Kolinummi

Juhani Vehvilainen

Mika Koikkalainen

Klaus Melakari

Marko Winblad

Erkki Nokkonen

Mike Jager

Juhani Vehvilänen

Juhani Vehviläinen

Tommi Kanerva

The invention relates to a method for enabling in a processing system a communication between at least two activated processes. In order to improve the communication between different processesof a processing system, it is proposed that for said communication signals are transmitted between said at least two processesin virtual channels using the same physical channel. This enables an efficient use of physical resources. A corresponding processing system comprises at least one processor-for running different processes, at least one physical channel provided for enabling a communication between at least two of said different processes, and means-for distributing signals which are to be transmitted for such a communication between said at least two different processes to different virtual channels on said at least one physical channel.

Method for enabling a communication between processes, processing system, integrated chip and module for such a chip

Suitably arranged circuits located on a die surface of respective multiple dies are operatively connected via a physical link, which is configured for full-duplex operation. Data information content is transferred between the operatively connected suitably arranged circuits via the full-duplex physical link which is configured as a fragmented data interconnected (FDI) physical link allowing peer-to-peer operation and pipelining. The data information content is carried in data fragments by a self-contained data packet structure. In one embodiment a device comprises a first suitably arranged and configured circuit located on a die surface, a second suitably arranged and configured circuit located on a die surface and a full-duplex physical link arranged and configured for operatively connecting the first circuit located on the die surface to the second circuit located on the die surface for transferring data information content between the first circuit and the second circuit.

Multiple die communication system

A device comprises an integrated circuit having first and second domains, the first domain having a first clock boundary module; and the second domain having a second clock boundary module. The first clock boundary module comprises: a buffer, for storing data for transfer to the second domain; and a first controller operable to send a first control signal to the second clock boundary module via a first synchronizer, the first control signal indicating the presence of a packet of data in a first storage location of the buffer. One of the first and second clock boundary modules comprises a multiplexer having an input connected to an output of the buffer and an output connected to circuitry forming part of the second domain. The second clock boundary module comprises: a second controller, operable in response to receiving the first control signal to control transfer of said data from the buffer by the multiplexer, and to send a second control signal to the first controller via a second synchronizer, the second control signal indicating transfer of said data.

Transferring data between asynchronous clock domains

An integrated circuit comprises a processor, a controller and plural terminals. Each terminal constitutes a connection between the integrated circuit and a peripheral device. Each terminal is connected to a logic circuit on the integrated circuit by a respective IO cell in series connection with a respective IO isolation circuit and wherein the controller is operable on power up of the integrated circuit to activate a reset state and to release the reset state prior to releasing IO isolation by one or more of the IO isolation circuits. Each IO isolation circuit may be arranged so that a default state of the IO isolation circuit is a state in which the IO cell is isolated from the logic circuit. The IO isolation circuits may be controllable by software, for instance a driver for a peripheral device connected to the terminal associated with the IO isolation circuit. Plural IO isolation circuits may be connected so as to be commonly controllable by a single control signal from the controller.

Integrated circuits

A method, system, module, apparatus, use, and computer program product are shown for determining a supply voltage level for operating an integrated circuit. To allow exact voltage level calibration, a high load condition is provided to the integrated circuit, a first voltage level of the integrated circuit is adjusted to provide a stable operation of the integrated circuit in the high load condition, a temperature of the integrated circuit in the high load condition is measured, the measured temperature in the high load condition is stored along with the adjusted first voltage level in the high load condition.

Adaptive voltage adjustment

The invention relates to a method in a hardware semaphore lock (L&#x2013;LN) intended for a multi-processor system, which semaphore lock (L&#x2013;LN) protects a shared resource (R&#x2013;RN) in connection with the system in such a way that only a process which has reserved the semaphore lock (L&#x2013;LN) and has thus become a holder of the lock, has access to use the resource protected by the lock. The semaphore lock (L&#x2013;LN) is reserved by a single read operation of a memory location representing the semaphore lock by the process software. The read operation returns to the process the number of vacant holder positions, i.e. keyholes vacant at the time of the reservation of the lock. The semaphore lock does not require the support of the system for atomic read/write operations.

Hardware semaphore intended for a multi-processor system

A method and device is disclosed for implementing dynamic power control in an electronic system implemented on an integrated circuit, which electronic system comprises at least one or several hardware units (), a hardware based power control logic () substantially implemented with logic circuits, as well as a programmable power control mode register () containing information about powered-down modes defined for said one or more hardware units. To transfer a single hardware unit () from the powered-down mode to the operational mode, the hardware unit transmits to the power control logic () a first level sensitive status signal () for transferring the hardware unit from the powered-down mode to the wake up mode, and further a second level sensitive status signal () for transferring the hardware unit from the wake up mode to the actual operating mode.

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Tampere, Finland

Pasi Kolinummi