Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Other

Leland Stanford Junior University

Centre National De La Recherche Scientifique

Institut National Polytechnique De Grenoble

Pascal Vivet

Edith Beigne

Didier Lattard

Fabien Clermidy

Marc Renaudin

Sébastien Thuries

Sylvain Miermont

Roman Gauchi

Patrice Senn

Yvain Thonnart

Jacky Bouvier

Olivier Billoint

Subhasish Mitra

Henri-Pierre Charles

Maha Kooli

Bettina Rebaud

Andr&eacute; Adrial

Hughes Metras

Julian Hilgemberg Pontes

Jérôme Quartana

The present description concerns a memory module () adapted to implementing computing operations, the module comprising a plurality of elementary blocks () arranged in an array according to rows and columns, wherein: each elementary block () comprises a memory circuit () adapted to implementing computing operations, and a configurable transfer circuit (); each configurable transfer circuit () is parameterizable to transmit data originating from a first transmit elementary block to a receive elementary block of a same column of elementary blocks via at least one link bus; an internal control circuit () is connected to an input-output port () of the module; and the internal control circuit () is configured to read at least one instruction signal from the input-output port () of the module and accordingly parameterize the configuration of the configurable transfer circuits (), and define the size of the operand vectors of the computing operations.

Reconfigurable memory module designed to implement computing operations

The present description concerns a memory device () comprising: a memory circuit () implementing operations and performing elementary operations including a reading, a writing, or a computing operation; a control circuit () receiving instructions from a processor (), and breaking down each received instruction into a plurality of elementary operations to generate an elementary operation request flow; a circuit () of direct data transfer from or to said memory circuit (), the transfer circuit () receiving instructions from the processor (), breaking down each received instruction into a plurality of elementary operations to be performed in said memory circuit to generate an elementary operation request flow; an internal data exchange link () directly coupling said memory circuit () to the direct transfer circuit (); and an arbitration circuit ().

Memory module adapted to implementing computing functions

A method of 3D circuit conception comprising: providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit; modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements; and performing, by the circuit conception tool, placement and routing of the 3D circuit design based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation.

Conception of a 3D circuit comprising macros

A tier of a 3D circuit comprising: one or more macro circuits, each macro circuit comprising a plurality of macro cells arranged in an array, the macro cells being separated from each other by spaces; and interconnection vias positioned in the spaces between the macro cells.

Integrated circuit comprising macros and method of fabricating the same

A two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit including: N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line independently of the voltage state of the other output lines.

Asynchronous data link

An asynchronous integrated circuit is designed from a library of cells comprising at least one cell having parameters of signal propagation between a first terminal and a second terminal and between the second terminal and a third terminal depending on the parameter of signal propagation between the first and the third terminal. A synchronous integrated circuit corresponding to the asynchronous integrated circuit is synthesized using said cell to represent a portion of the asynchronous circuit, said cell being rated by a dummy clock signal. The synthesized integrated circuit is verified using the parameter of signal propagation between the first terminal and the third terminal to simulate the operation of said portion of the asynchronous circuit.

Cell library and method for designing an asynchronous integrated circuit

A device for powering an electronic circuit that applies at least a first voltage or a second voltage, different from the first voltage, to the electronic circuit. The device includes a performance monitor that receives an item of information defining a constraint and determines a first duration and a second duration, such that the operation of the electronic circuit at a first frequency associated with the first voltage for the first duration, and at a second frequency associated with the second voltage for the second duration, complies with the constraint. The device applies the first voltage and the first frequency to the circuit for the first duration and the second voltage and the second frequency for the second duration.

Device for powering an electronic circuit, in particular a digital circuit, and associated method

An electronic circuit power supply device configured to selectively apply at least one first voltage or one second voltage to a power supply terminal of the electronic circuit that includes elements for applying to the power supply terminal a voltage variable from a value equal to the first voltage to a value equal to the second voltage and elements designed for selecting application of the second voltage to the power supply terminal when the variable voltage reaches the second voltage.

Electronic circuit power supply device and electronic circuit

This invention relates to the domain of Networks on Chips (NoC) and relates to a method of transferring data in a network on chip, particularly using an asynchronous 'send/accept' type protocol. The invention also relates to a network on chip used to implement this method.

Globally asynchronous communication architecture for system on chip

A network and a data transmission method between elements in such a network using an asynchronous communication protocol of the 'send/accept' type. At least one node in the network operations without an internal clock, this node determining a transfer hierarchy between two data packets to be routed to the same output, at least as a function of a priority channel information associated with each data packet.

Communication node architecture in a globally asynchronous network on chip system

A micro-electronic component for a portable object is of the type which incorporates digital processing means, and an interface for contact-free electromagnetic coupling with a remote station. The digital processing means can operate according to an operating mode of the request/acknowledgement type, which is substantially insensitive to the propagation time, without a global, regular clock. The component additionally comprises adapter means, which can adapt the signals of the contact-free interface to the signals of the digital processing means and vice versa, in order to permit two-way dialogue with the remote station.

Growing community of inventors

Saint Paul de Varces, France

Pascal Vivet