Stmicroelectronics S.a.

Stmicroelectronics International N.v.

Stmicroelectronics (crolles 2) Sas

Centre National De La Recherche Scientifique

Stmicroelectronics France

Stmicroelectroncis Sa

Centre National De La Recherche Scientifique-cnrs

Pascal Urard

Laurent Paumier

Vincent Heinrich

Alok Kumar Tripathi

Kallol Chatterjee

Nitin Chawla

Chittoor Parthasarathy

Daniel Gloria

Olivier Hinsinger

Christophe Regnier

Yan Meroth

Nicolas Le Dortz

Thierry Simon

Caroline Lelandais-Perrault

Kedar Janardan Dhori

Promod Kumar

Patrizia Milazzo

Olivier Weber

David Declercq

Vincent Huard

Amit Verma

Christophe Lecocq

Marc P Fossorier

Shafquat Jahan Ahmed

Séverin Trochut

Florian Cacho

Philippe Coussy

Cyrille Chavet

Eric Martin

Philippe Cavenel

Lionel Balme

Martial Comminges

Etiene Lantreibecq

Thierry Valentin

Mauricio Garcia Suarez

Charlotte Beylier

Guillaume Landie

Rakhel Kumar Parida

Fabien Todeschini

Christophe Planat

Salvatore Tricomi

Adrian Voicila

François Verdier

Marc Fossorier

The present description concerns a method that includes the compression, by a processor, of an image comprising first patterns by transforming the image into a first representation formed of two-point elements. The method also includes the execution, by a neural network, of an inference operation on the first representation to generate a second representation formed of two-point elements. The method further includes the generation of a lithographic mask based on the decompression of the second representation.

Device and method for generating photomasks

In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.

Silicon-on-insulator semiconductor device with a static random access memory circuit

A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.

Flip flop of a digital electronic chip

The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

Method for managing the operation of a synchronous retention flip-flop circuit exhibiting an ultra-low leakage current, and corresponding circuit

A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.

Method for managing the operation of a low-complexity synchronous retention flip-flop circuit, and corresponding circuit

A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit.

Wireless device pairing

A device can be used for compensating bandwidth mismatches of time interleaved analog to digital converters. A processor of the device determines, for each original sample stream, an estimated difference between the time constant of a low pass filter representative of the corresponding converter and a reference time constant of a reference low pass filter, and uses this estimated difference and a filtered stream to correct the original stream and deliver a corrected stream of corrected samples.

Method and device for compensating bandwidth mismatches of time interleaved analog to digital converters

A power management circuit including, between a first terminal intended to be connected to an electric power generation source and a second terminal intended to be connected to a load to be powered, a linear regulator and a circuit capable of activating the linear regulator when the power supplied by said source is greater than a first threshold.

Power management circuit for a self-powered sensor

A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device.

Photovoltaic device with through-vias

Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Adaptive multi-stage slack borrowing for high performance error resilient computing

According to one mode of implementation, a method includes an estimation including on the one hand a correlation processing involving at least one part of the sampled signal, at least one part of at least one first signal gleaned from a derived signal representative of a temporal derivative of the sampled signal and at least one part of N partial filtered signals respectively representative of N weighted differences between N pairs of bracketing versions flanking the sampled signal, N being greater than or equal to 1. On the other hand, the estimation includes a matrix processing on the results of this correlation processing. Correction processing of the M&#x2212;1 trains involves respectively M&#x2212;1 second signals gleaned from the derived signal and the suite of M&#x2212;1 shift coefficients.

Method and device for use with analog to digital converter

A barrel shifter receiving N symbols, arranged ndistinct groups of nsymbols, applying a circular shift to the N symbols. The barrel shifter comprises nfirst barrel shifters, each applying a first circular shift to one of the groups of nsymbols; a rearrangement module receiving the N symbols provided by the first barrel shifters and providing N symbols arranged, in a determined manner, in ndistinct groups of nsymbols; nsecond barrel shifters, each applying a second circular shift to one of the distinct groups of nsymbols; a control module providing, to each first barrel shifter, an identical signal bs_ctrlrepresenting the first shift, and providing, to each second barrel shifter, an identical signal bs_ctrlrepresenting the second shift; and a switching module switching at least two of the symbols of the N symbols.

Barrel shifter

A string of K initial symbols is encoded with a code of the parity check type. The K initial symbols belong to a Galois field of order q strictly greater than 2. The code is defined by code characteristics representable by a graph (GRH) comprising N&#x2212;K first nodes (NC), each node satisfying a parity check equation defined on the Galois field of order q, N packets of intermediate nodes (NIT) and NI second nodes (NSS), each intermediate node being linked to a single first node and to several second nodes by way of a connection scheme. The string of K initial symbols is encoded by using the said code characteristics and a string of N encoded symbols is obtained, respectively subdivided into NI sub-symbols belonging respectively to mathematical sets whose orders are less than q, according to a subdivision scheme representative of the connection scheme (&#x3a0;).

Method and device for encoding symbols with a code of the parity check type and corresponding decoding method and device

Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.

Method for decoding a succession of blocks encoded with an error correction code and correlated by a transmission channel

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Theys, France

Pascal Urard