International Business Machines Corporation

Stmicroelectronics S.a.

Pascal R Tannhof

Ali Ghassan Saidi

Kerry A Kravec

Jan M Slyfield

Ghislain Imbert De Tremiolles

Pierre B Mollier

Andre R Steimle

Didier R Louis

Guy Paillet

Erwan Dornel

Seiki Ogura

Clark Debs Jeffries

Ravinder Kumar Sabhikhi

Simon Jeannot

Denis Rideau

Gerard Boudon

Jean-Paul J Nuez

Catherine Godefroy

Marc A Boulanger

C Marcel Kinard

Franck Wallart

Jean-Yves Boulet

Myriam Combes

Dominique P Bonneau

Dominique M Omet

Anthony J Dally

Matthew Lee Helsley

Ieng Ong

Davide Garetto

Gislain Imbert De Tremiolles

Erin Williams

Andr&eacute; Steimle

A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.

Method for forming a three-dimensional structure of metal-insulator-metal type

Embodiments of the present invention provide a memory array of macro cells. Each macro cell comprises a storage element and a calibration element. The storage element and its corresponding calibration element are part of a common memory array within an integrated circuit, and therefore, are in close proximity to each other. The calibration element may store a parameter used to modify the threshold voltage of the storage element.

Structure and method for narrowing voltage threshold distribution in non-volatile memories

A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.

Metal oxide semiconductor (MOS) device with locally thickened gate oxide

An intrusion detection system (IDS) comprises a network processor (NP) coupled to a memory unit for storing programs and data. The NP is also coupled to one or more parallel pattern detection engines (PPDE) which provide high speed parallel detection of patterns in an input data stream. Each PPDE comprises many processing units (PUs) each designed to store intrusion signatures as a sequence of data with selected operation codes. The PUs have configuration registers for selecting modes of pattern recognition. Each PU compares a byte at each clock cycle. If a sequence of bytes from the input pattern match a stored pattern, the identification of the PU detecting the pattern is outputted with any applicable comparison data. By storing intrusion signatures in many parallel PUs, the IDS can process network data at the NP processing speed. PUs may be cascaded to increase intrusion coverage or to detect long intrusion signatures.

Intrusion detection using a network processor and a parallel pattern detection engine

The method and circuits of the present invention aim to associate a complex component operator (CC_op) to each component of an input pattern presented to an input space mapping algorithm based artificial neural network (ANN) during the distance evaluation process. A complex operator consists in the description of a function and a set of parameters attached thereto. The function is a mathematical entity (either a logic operator e.g. match(Ai,Bi), abs(Ai&#x2212;Bi), . . . or an arithmetic operator, e.g. &#x3e;, &#x3c;, . . . ) or a set of software instructions possibly with a condition. In a first embodiment, the ANN is provided with a global memory, common for all the neurons of the ANN, that stores all the CC_ops. In another embodiment, the set of CC_ops is stored in the prototype memory of the neuron, so that the global memory is no longer physically necessary. According to the present invention, a component of a stored prototype may now designate objects of different nature. In addition, either implementation significantly reduces the number of components that are required in the neurons, therefore saving room when the ANN is integrated in a silicon chip.

Method and circuits for associating a complex operator to each component of an input pattern presented to an artificial neural network

An artificial neural network (ANN) based system that is adapted to process an input pattern to generate an output pattern related thereto having a different number of components than the input pattern. The system () is comprised of an ANN () and a memory (), such as a DRAM memory, that are serially connected. The input pattern () is applied to a processor (), where it can be processed or not (the most general case), before it is applied to the ANN and stored therein as a prototype (if learned). A category is associated with each stored prototype. The processor computes the coefficients that allow the determination of the estimated values of the output pattern, these coefficients are the components of a so-called intermediate pattern (). Assuming the ANN has already learned a number of input patterns, when a new input pattern is presented to the ANN in the recognition phase, the category of the closest prototype is output therefrom and is used as a pointer to the memory. In turn, the memory outputs the corresponding intermediate pattern. The input pattern and the intermediate pattern are applied to the processor to construct the output pattern () using the coefficients. Typically, the input pattern is a block of pixels in the field of scaling images.

System for scaling images using neural networks

A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into each of the processing units and a distance defining the similarity between the reference pattern and each of the input patterns is calculated. A present calculated distance replaces its corresponding stored present minimum distance if it is has a smaller value. After the R reference patterns have been processed the minimum distance and its corresponding identification for all N input patterns is determined without merging outputs. The minimum distances and the identifications may be read either in parallel or serially. The apparatus is easily scalable by adding processors. The number of reference patterns may be easily increased without altering system configuration.

Apparatus for performing fast closest match in pattern recognition

A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.

Parallel pattern detection engine

Method and apparatus for performing fast closest match in pattern recognition

Method and circuits for scaling images using neural networks

An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.

Method and circuits to virtually increase the number of prototypes in artificial neural networks

Growing community of inventors

Fontainebleau, France

Pascal R Tannhof