International Business Machines Corporation

Globalfoundries Inc.

Pascal P Blais

Clement J Fortin

Jae-Woong Nah

Paul Francis Fortier

Kang-Wook Lee

Luc Gilbert Guerin

Soojae Park

Christian Bergeron

Alain A Warren

Robert L Toutant

A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.

Method of joining a chip on a substrate

A reflow method for solder includes heating the solder to a first temperature that is above a liquidus temperature of the solder; cooling the solder to a second temperature that is below a solidification temperature of the solder; reheating the solder to a third temperature that is above a solidus temperature of the solder and below the liquidus temperature of the solder; cooling the solder to a fourth temperature that is below the solidification temperature of the solder.

Reflow method for lead-free solder

A method for verifying the internal microstructure of interconnects in flip-chip applications includes providing a microelectronic assembly comprising the following: a substrate hosting an array of flip-chip attach pads and one or more process control pads; a flip chip having an array of solder bumps in contact with the array of flip-chip attach pads; and one or more representative solder bumps contacting the one or more process control pads. The representative solder bumps have a substantially similar or identical chemical composition as the array of solder bumps. A reflow cycle is then applied to the microelectronic assembly to melt and solidify the array of solder bumps on the flip-chip attach pads and melt and solidify the representative solder bumps on the process control pads. The surface texture of the representative solder bumps is then optically inspected to determine an internal microstructure of the array of solder bumps.

Technique for verifying the microstructure of lead-free interconnects in semiconductor assemblies

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Shefford, Canada

Pascal P Blais