Stmicroelectronics S.a.

Sgs-thomson Microelectronics Limited

Other

Pascal Moniot

Marcello Coppola

Neil Richards

Robert John Simpson

David Mouen Makoua

Pierre Dumas

Peter Thompson

Thierry Grenot

David Furodet

Vincent Roca

Christoph Neumann

Aurélien Francillon

Vincent Cottignies

The invention concerns a method and a system for encoding digital data (DATA) represented by source symbols, with an error correcting code generating parity symbols from, for each parity symbol, a plurality of source symbols and at least one parity symbol of preceding rank, including at least encrypting once () at least one first value (P) into several encrypted values and integrating at least one combination (P) of said encrypted values to compute () at least one part (P. . . P) of said parity symbols.

Secure transmission with error correcting code

A method and a system for coding digital data represented by source symbols (Si) with an error-correction code. The error-correction code generates parity symbols (Pj) based on, for each parity symbol, several source symbols and at least one parity symbol of preceding rank. At least a part of the source symbols is submitted to at least a first ciphering. The obtained ciphered symbols and the rest of the unciphered source symbols are submitted to the error-correction code.

Method for ciphering data with error correction code

A method for providing a context datum associated with a source and/or destination device based on an address datum associated with the device, including addressing, based on the address datum, a unit for providing an index, the unit containing, for each address datum, an indicator indicating whether the device is active; and addressing, based on the index provided by the unit, a context memory for providing the context datum associated with the device.

Method and circuit for providing a context datum of a device based on an address associated with this device

A method for associating with a first address a second address of reduced size, comprising: calculating a first intermediary address by the first address, the first intermediary address having a reduced size with respect to the first address; then choosing as a second address the first intermediary address if this second address is not associated with another first address, or, otherwise, calculating a second intermediary address by a first polynomial division of the first address, the second intermediary address having a reduced size as compared to the first address; then choosing as a second address the second intermediary address.

Method for associating a first address with a second address of reduced size for directly addressing a context memory on a computer

A method is provided for controlling the rates of concurrent digital transmissions using at least a first queue having a plurality of locations. For each transmission, an index corresponding to a data cell of the transmission is written at one of the locations in the first queue, and the locations of the first queue are successively surveyed at a rate corresponding to a cell transmission rate. If the surveyed location in the first queue contains an index, the corresponding data cell is transmitted, the location is freed, and the index is rewritten at the location in the first queue that is distant from the surveyed location by a value determined by the rate of the corresponding transmission. In one preferred method, indexes corresponding to high priority transmissions are written into the first queue and indexes corresponding to lower priority transmissions are written into a second queue. Also provided is a method for controlling the rates of concurrent digital transmissions using at least first and second queues.

System for controlling the rates of concurrent transmissions on a communication channel

A device for associating indexes to addresses chosen from among a greater number of values than the number of available indexes, including a memory containing indexes and respective check words corresponding to predetermined bits of the addresses associated with the indexes; a packing circuit receiving a current address and suppressing in this address bits determined by a pattern such that the suppressed bits correspond to bits of the check words, the packed address provided by the packing circuit being used to select in the read mode a memory location; and a comparator indicating that the current address corresponds to the selected memory location if the bits of the check word of the selected location are equal to the corresponding bits of the current address.

Device for associating indexes to addresses chosen from a greater number than the number of available indexes

A buffer for adapting data flows from input channels to output channels is provided. The buffer includes a DRAM organized in blocks and a memory controller for managing assignment of the blocks to the chains of linked blocks. The DRAM contains, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, and also contains a main queue of free blocks for listing unoccupied blocks. The memory controller includes a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment. According to one embodiment, when a level of the partial queue reaches a predetermined minimum limit the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit the cache memory is at least partially emptied by a burst into the main queue. According to another embodiment, the partial queue stores a local image of a top portion of the main queue, and the memory controller exclusively uses the partial queue in assigning blocks to the chains of linked blocks. Further embodiments of the present invention provide methods of managing a buffer.

Buffer associated with multiple data communication channels

An ATM routing switch has a buffer circuit for holding cells located on queues at output ports, the buffer having a first reserve buffer capacity for cells of a first type requiring integrity of cell transmission and a first designation for use in determining a permitted path through the network, a second reserve buffer capacity for cells of the first type having a second designation for use in determining a different permitted path in the network and a third reserve buffer capacity for cells of a second type accepting some loss of cells in transmission, flow control circuitry operating to limit input of cells of either the first or second type if predetermined thresholds for the first, second or third buffer capacities are reached.

ATM switch for routing different cell types

An ATM routing switch has a plurality of output ports for handling digital signal cells on a first type requiring integrity of cell transmission and a second type accepting some loss of cells in transmission, the output ports having control circuitry to provide a plurality of queues of cells at each output port, each queue comprising only cells of a single type while each port outputs a mixture of cells of both types on a common output path flow control indicators on incoming cells being used to inhibit output of cells along any path to a destination for which a flow control indicator has indicated congestion.

Congestion avoidance in an ATM switch

An ATM routing switch for bidirectional transmission of at least two types of cell, one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity for cells of the first type, a second reserve buffer capacity for cells of said second type and control circuitry for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity is reached by input of cells of said first type, and discarding input cells of said second type if a predetermined threshold for said second buffer capacity has been reached by input of cells of said second type.

ATM switch

An ATM routing switch has a plurality of input and output ports and a buffer for holding a plurality of ATM cells, the cells being held in the buffer as a plurality of queues (F0-F7), each formed as a chained list of addresses with front and back pointers identifying ends of each queue.

Cell queue formation in an ATM switch

A network of ATM routing switches transmits digital signal cells of a first type requiring integrity of transmission and a second type accepting some loss in transmission, each switch has buffer circuitry. a plurality of output ports each having a plurality of queues of cells awaiting output, each output port having control circuitry to provide in an output frame control bits indicating the type of cell, a path identifier and the existence of flow congestion at the routing switch which it outputting the frame, thereby inhibiting transmission of further frames to that location until a frame is received from that location indicating that the congestion is cleared.

ATM switch flow control

An ATM routing switch for bidirectional transmission of digital signal cells some requiring integrity of transmission while others accept some loss of cells in transmission, has a plurality of output ports each handling a plurality of cell queues and control circuitry for decoding control bits in each input cell to determine which output port is to be used, which queue is required and whether flow congestions exists at the source of the input cell.

Growing community of inventors

Bernin, France

Pascal Moniot