Intel Corporation

Bar-ilan University

Pascal Meinerzhagen

Muhammad M Khellah

Minki Cho

Anupama Ambardar Thaploo

Suyoung Bang

Stephen Kim

Vivek K De

Jaydeep P Kulkarni

Charles Augustine

Iqbal Rajwani

Alexander Fish

Adam Teman

Robert Giterman

Andreas Burg

James W Tschanz

Bhushan M Borole

Carlos Alfonso Tokunaga

Arvind Raman

Sandip Kundu

Gururaj Shamanna

Lei Jiang

Yong Shim

Karthik Subramanian

Abdullah Afzal

Jagadeesh Chandra Salaka

Naveen Kumar M

Dongmin Yoon

Suphachai Chai Sutanthavibul

Surya Sasi Kiran Tallapragada

Daivik H Bhatt

Andrea Bonetti

Sravan K Puchakayala

Circuits for optimizing the duration of a sense amp enable signal in a memory device such as SRAM.

Apparatus and method to optimize sense-amp enable pulse-width in SRAM arrays

Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).

Unified retention and wake-up clamp apparatus and method

An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.

Reliable digital low dropout voltage regulator

A minimum delay error apparatus such as a minimum delay error detection, prediction, correction, repair, prevention, and/or avoidance apparatus includes a minimum delay path replica circuit. The minimum delay path replica circuit can detect or predict, and subsequently can correct or avoid, minimum delay errors in data paths of digital circuits using pulsed latches.

Minimum delay error detection and correction for pulsed latches

An apparatus is provided which comprises: a first power supply rail to provide a first power supply voltage; a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage; a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first supply voltage, and wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication; and a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.

Charge injector with integrated level shifter for localized mitigation of supply voltage droop

Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

Calibrated biasing of sleep transistor in integrated circuits

An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.

Apparatus for data retention and supply noise mitigation using clamps

Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.

Multi-bit pulsed latch including serial scan chain

Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.

Power switching circuitry including power-up control

Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.

Voltage level shifter monitor with tunable voltage level shifter replica circuit

A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.

Transistor gain cell with feedback

Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal; a resistive device; a first transistor coupled in series with the resistive device together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor; a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.

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A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.

Described are apparatuses and methods for detecting or repairing minimum-delay errors. The apparatus may include a minimum-delay error detector (MDED) to receive a clock signal and a data path signal and to detect a minimum-delay error (MDE) in the data path based on the received data path signal and the clock signal. The MDE may be repaired by adjusting one or more regional clock buffers coupled to the MDED. Further, the apparatus may include minimum-delay path replicas (MDPRs) used for detecting and repairing MDEs during normal system operations. Other embodiments may be described and/or claimed.

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Hillsboro, OR, United States of America

Pascal Meinerzhagen