Motorola Corporation

Pascal Leclercq

David T Jobling

Laurent Tran

Olivier Pilloud

A data receiver is arranged to receive data comprising a sync word having a predetermined data frequency (f.sub.tx) and predetermined value. A clock signal (SCLK) is generated which is substantially synchronised with the received data. The n clocks (CLK1-CLK8) are generated, each of the n clocks having a frequency (fclk) which is substantially the predetermined data frequency (f.sub.tx) and is out of phase with an adjacent clock of the n clocks by 1/n of a clock period. The sync word is sampled using each of the n clocks to determine which one of the n clocks is optimally synchronised with the sync word and to provide the determined one of the n clocks at an output (18). The determined one of the n clocks provides the clock signal (SCLK).

Growing community of inventors

Fresnes, France

Pascal Leclercq