Stmicroelectronics (rousset) Sas

Stmicroelectronics S.a.

Pascal Fornara

Christian Rivero

Fabrice Marinet

Guilhem Bouton

Antonio Di-Giacomo

Abderrezak Marzaki

Mathieu Pierre Lisart

Brice Arrazat

Roberto Simola

Francesco La Rosa

Yoann Goasduff

Virginie Bidal

Arnaud Regnier

Jean-Philippe Escales

Sebastian Orellana

Philippe Boivin

Stephan Niel

Julien Delalleau

Albert Martinez

Quentin Hubert

Laurent Lopez

Olivier Pizzuto

Matthias Vidal-Dho

A method for detecting orientation of an integrated circuit is disclosed. The method includes moving, in response to a gravitational force, a mobile metallic piece in an evolution zone of a housing. The housing is formed in an interconnect region of the integrated circuit. The housing includes walls defining the evolution zone. The walls are formed within multiple metallization levels of the interconnect region. The walls include a floor wall and a ceiling wall. At least one of the floor wall and ceiling wall incorporate a pointed element directing its pointed region towards the mobile metallic piece. The pointed element delimits an open crater in a concave part of a projection. The method further includes creating an electrical signal by movement of the mobile metallic piece at a plurality of electrically conducting elements positioned at boundary points of the evolution zone and detecting the electrical signal by a detector.

Method for producing an integrated circuit pointed element comprising etching first and second etchable materials with a particular etchant to form an open crater in a projection

Methods of operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.

Electrically controllable integrated switch

An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

Method for protecting data stored in a memory, and corresponding integrated circuit

A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.

Integrated fuse

An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

Integrated circuit including a capacitive structure of the metal-insulator-metal type and corresponding manufacturing method

An integrated circuit includes a first substrate. A MOS transistor has a first polysilicon region electrically isolated from the first substrate and including a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and from the first substrate. The second polysilicon region includes a source region, a substrate region and a drain region of the MOS transistor. The first polysilicon region is located between an area of the first substrate and the second polysilicon region.

MOS transistor isolated from the substrate of an integrated circuit and application for detecting an opening of a closed container

An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

Integrated ultralong time constant time measurement device and fabrication process

A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.

Pin diode including a conductive layer, and fabrication process

A method of operating a mechanical switching device is disclosed. The switching device includes a housing, an assembly disposed in the housing, and a body. The assembly is thermally deformable and comprises a beam held in two different places by two arms secured to edges of the housing. The beam is remote from the body in a first configuration and in contact with and immobilized by the body in a second configuration. The assembly has the first configuration at a first temperature and the second configuration when one of the arms has a second temperature different from the first temperature. The method includes exposing an arm of the assembly to the second temperature, and releasing the beam using a release mechanism. The release mechanism includes a pointed element comprising a pointed region directed towards the body. The pointed element limits an open crater in a concave part of a projection.

Method for producing an integrated circuit pointed element comprising etching first and second etchable materials with a particular etchant to form an open crater in a project

Moisture that is possibly present in an integrated circuit is detected autonomously by the integrated circuit itself. An interconnect region of the integrated circuit includes a metal level with a first track and a second track which are separated by a dielectric material. A detection circuit applies a potential difference between the first and second tracks. A current circulating in one of the first and second tracks in response to the potential difference is measured and compared to a threshold. If the current exceeds the threshold, this is indicative of the presence of moisture which renders said dielectric material less insulating.

Method for detecting moisture in an integrated circuit, and associated integrated circuit

An integrated circuit includes a circuit module storing sensitive data. An electrically conductive body at a floating potential is located in the integrated circuit and holds an initial amount of electric charge. In response to an attack attempting to access the sensitive data, electric charge is collected on the electrically conductive body. A protection circuit is configured to ground an output of the circuit module, and thus preclude access to the sensitive data, in response to collected amount of electric charge on the electrically conductive body differing from the initial amount and exceeding a threshold.

Method for protecting an integrated circuit module using an antifuse, and corresponding device

An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.

Method for protecting an integrated circuit, and corresponding device

An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

Growing community of inventors

Pourrieres, France

Pascal Fornara