Elonex IP Holdings Ltd.

Elonex Technologies, Inc.

Cordata Incorporated

Elonex Plc

Consilium Overseas Limited

Elonex F.p. Holdings, Ltd.

Elonex IP Hudings, Ltd.

Eloner I.p. Holdings Ltd.

Elougx I.p. Holdings L.t.d.

Pascal Dornier

Dan Kikinis

William J Seiler

William S Jocobs

William J Seiller

William S Jacobs

A personal digital assistant module with a local CPU, memory, and I/O interface has a host interface comprising a bus connected to the local CPU and a connector at a surface of the personal digital assistant for interfacing to a bus connector of a host general-purpose computer, providing direct bus communication between the personal digital assistant and the host general-purpose computer. In an embodiment, the personal digital assistant also has a means for storing a security code. The personal digital assistant according to the invention forms a host/satellite combination with a host computer having a docking bay, wherein upon docking a docking protocol controls access by the host to memory of the personal digital assistant based on one or more passwords provided by a user to the host. In another embodiment the personal digital assistant has a compressed BIOS chip, and in yet another embodiment also has an expansion port connected to the local CPU, and expansion peripheral devices may be connected and operated through the expansion port.

Micropersonal digital assistant

An IDE interface communicates with peripheral devices not conforming to ST506 specification by providing firmware to microcontrollers mounted on the non-conforming peripheral devices to translate between the data structure of an ST506 specification device and the data structure of the non-conforming device. CD-ROM and cartridge tape drive communication is provided. An enhanced IDE interface communicates with multiple peripheral devices by adding a selective ability to the firmware of the conventional IDE interface.

Peripheral device control through integrated drive electronics

A system for reducing power consumption of a computer peripheral device connected to a host computer during periods of inactivity of the host computer has a dedicated input for initiating power management operations. When the dedicated input is sensed a timer is started and a power management command is sent to the peripheral device, initiating a reduced-power mode other than off. In a preferred embodiment the system also starts a timer when the dedicated input is sensed, and after a predetermined time a second power management command is sent triggering a second reduced-power mode for the peripheral. The system is adapted to peripheral devices such as video displays and printers.

Computer peripherals low-power-consumption standby system

A system for managing power levels for a general purpose computer having a standby and a full-power mode of operation provides apparatus and a method for monitoring times of user input and control routines for using the times of user input to calculate optimum times for initiating full power operation and standby mode. The control routines are configured to provide the optimum times to a real time clock that remains powered in the standby mode, which triggers switching elements to initiate full power and standby mode. In one embodiment of the system, startup and standby may be initiated either by user input or automatically by the power management system. Startup and standby initiation times may be different for different days and time periods based on both preprogrammed and calculated values.

Timer-controlled computer system shutdown and startup

An integrated CPU has an on-board switching voltage regulator with an electrically-erasable programmable read-only memory electronically accessible for storing a feedback reference coefficient for control. In further embodiments, output voltage is tuned via a second EEPROM storing an electronically accessible value in concert with a solid-state resistor ladder. In other embodiments, signals on interrupt lines to the CPU are monitored to provide a prewarning of impending activity by the CPU requiring dramatically increased current flow. In yet other embodiments, solid state circuitry is provided to reduce or eliminate capacitors used for dealing with input current surges to the CPU.

Variable-voltage CPU voltage regulator

A disk array server has a cache and a log drive wherein data blocks, as received are written synchronously to both the cache and the log drive, the cache being written back to the disk array as opportunity affords. The log drive is managed so, when full, data is overwritten in the order first stored on the log drive. Data blocks written to the log drive are flagged as to whether the same block in cache has been written to the disk array, and the flags are updated as the cache is written back to the disk array. In the event of a power failure, data lost from the volatile cache as not yet written to the disk array may be recovered from the log drive. In one embodiment, the recovery is automatic on startup after a power failure.

Disk array controller with enhanced synchronous write

A miniature digital assistant module with a local CPU, a memory, and a touchscreen I/O interface in a preferred embodiment, has a host interface comprising a full-service parallel bus, including data lines, address lines, read/write signals, and at least one memory control signal, connected to the local CPU and also to a connector at a surface of the personal digital assistant. The full-service bus connection provides direct bus communication between the personal digital assistant and a host computer. In a preferred embodiment, the miniature digital assistant also stores a security code, which the host can recognize. The miniature digital assistant forms a host/satellite combination with the host computer, which has a docking bay. When the miniature digital assistant is docked, a docking control routine controls access by the host to memory of the personal digital assistant based on one or more passwords provided by a user to the host. In an alternative embodiment the personal digital assistant also has an expansion port connected to the local CPU, and expansion peripheral devices may be connected and operated through the expansion port, even while the miniature digital assistant is docked.

Miniature digital assistant having enhanced host communication

A system for lowering the power output of a computer peripheral device connected to a host computer during periods of inactivity of the host or the peripheral device senses a power management command at the peripheral device generated at the host computer. Time sensing means at the host senses inactivity, and gerating circuitry generates a power-management command. Detection circuitry in the peripheral device senses the power-management command, and controls power-using circuitry in the peripheral device in response. In an embodiment applicable to peripherals having a microprocessor, the system may be incorporated entirely in software at the host and the peripheral device. In dumb devices, the system requires add-in and/or add-on apparatus cooperating with software.

A personal digital assistant module with a local CPU, (central processing unit) memory, and I/O (input/output) interface has a host interface comprising a bus connected to the local CPU and a connector at a surface of the personal digital assistant for interfacing to a bus connector of a host general-purpose computer, providing direct bus communication between the personal digital assistant and the host general-purpose computer. In an embodiment, the personal digital assistant also stores a security code. The personal digital assistant according to the invention forms a host/satellite combination with a host computer having a docking bay, wherein upon docking a docking protocol controls access by the host to memory of the personal digital assistant based on one or more passwords provided by a user to the host. In another embodiment the personal digital assistant also has an expansion port connected to the local CPU, and expansion peripheral devices may be connected and operated through the expansion port. Connectable devices may include input devices such as pointer devices, that may in some cases be stored in a compartment fashioned for the purpose in the personal digital assistant.

Personal digital assistant module having a broadcast pointer device

A digital assistant computer device has an audio input interface and a memory adapted to receive audio input of significant time extent, and to convert the input and store it as a digital sound file. The digital assistant in one embodiment has a CPU and bus, input and display apparatus, on-board memory, and a microphone and digital signal processor for accepting and converting audio input. In some such embodiments the on-board memory is flash memory

Personal organizer with interface for recording digital voice files

Enhanced integrated device electronics (EIDE) interface for controlling

An interrupt control circuit for use in a computer system has a CPU, a peripheral I/O device, and a bus having address lines for carrying signals to and from the peripheral I/O device. Interrupt requests generated by the I/O device are encoded as address signals which are transmitted on the address bus lines. A predetermined set of addresses are set aside to represent the interrupt requests. The interrupt control circuit is coupled to the address bus lines to receive the encoded interrupt requests. The interrupt control circuit has an address decoder which receives address signals from the I/O device. When these address signals represent an address within the predetermined set of addresses set aside to represent the interrupt requests, the address decoder uses the address signals to create a plurality of interrupt control signals. The interrupt control signals are provided to an interrupt latch/decoder which uses the interrupt control signals to create interrupt request signals. The interrupt request signals are provided to an interrupt controller. In response, the interrupt controller and the CPU process the interrupt request.

Structure and method for issuing interrupt requests as addresses and for

A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to 'high' memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM allowing various models and types of CPUs to be supported. Supported CPUs are interchangeable in the system. In another aspect a default interface attached to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.

Structure and method for mapping interrupt requests in a high-speed CPU

A business telephone system employs digital signal processing in a digital telephone having a serial link for connection to a general-purpose computer. The Smart Phone is the central intelligence for the system, which may utilize a PBX connected in a LAN network to multiple computers, including file servers, and each computer may have one or more Smart Phones connected. In one embodiment, docking bays in the phone provide an ability to interchange functional modules, including DSP modules. The docking bays and functional modules may be configured to PCMCIA standards. In another embodiment, a docking bay, which may also be PCMCIA, has a physical window allowing access to an input area on a docked module, wherein the docked module is an intelligent module with a CPU, a memory, and a bus structure, affording control of the smart phone and the entire system through the input interface of the docked module. In various embodiments the external form of the system may vary, and in one embodiment, the smart phone elements are integrated with a desktop or a portable computer having docking bays to receive and connect functional modules, such a DSP modules and/or an intelligent module.

Smart phone integration with computer systems

A business telephone system employs digital signal processing in a digital telephone having a serial link for connection to a general-purpose computer. The Smart Phone is the central intelligence for the system, which may utilize a PBX connected in a LAN network to multiple computers, including file servers, and each computer may have one or more Smart Phones connected. In one embodiment, docking bays in the phone provide an ability to interchange finctional modules, including DSP modules. The docking bays and functional modules may be configured to PCMCIA standards. In another embodiment, a docking bay, which may also be PCMCIA, has a physical window allowing access to an input area on a docked module, wherein the docked module is an intelligent module with a CPU, a memory, and a bus structure, affording control of the smart phone and the entire system through the input interface of the docked module. In various embodiments the external form of the system may vary, and in one embodiment, the smart phone elements are integrated with a desktop or a portable computer having docking bays to receive and connect functional modules, such a DSP modules and/or an intelligent module.

Growing community of inventors

Sunnyvale, CA, United States of America

Pascal Dornier