Stmicroelectronics S.a.

Sgs-microelectronics S.a.

Pascal Couteaux

Roland Marbot

Reza Nezamzadeh

Jean-Claude Le Bihan

Michel D'Hoe

Francis Mottini

Anne Pierre-Duplessix

Anne Pierre Duplessix

A testing device for testing dynamic characteristics of an electronic circuit using serial transmissions. The circuit includes a multiplexing device and a demultiplexing device for implementing a serial link in the component or circuit. The testing device includes a transmitter for transmitting binary signals to the multiplexing device, a receiver for receiving binary signals from the demultiplexing device, and a link for selectively providing a coupling between the transmitter and the receiver. Additionally, a clock generator delivers a first clock signal to the transmitter and a second clock signal, which has a different frequency than the first clock signal, to the receiver. In one preferred embodiment, the clock generator includes a single programmable-frequency oscillator and a variable delay circuit. The programmable-frequency oscillator delivers the first clock signal and the variable delay circuit delays the first clock signal to deliver the second clock signal. The testing device can be used with circuits operating at frequencies in the range of 100 MHz. A method of testing dynamic characteristics of an electronic circuit using a testing device is also provided.

Device for testing dynamic characteristics of components using serial transmissions

Disclosed is a device for the conversion of a series signal received in the form of a low-amplitude, high-frequency differential signal into n parallel signals. The device uses a scheme derived from that of a static memory cell as a sample-and-hold unit and amplifier. The device continues to perform well when the differential signal comprises noise in common mode.

System for series to parallel conversion of a low-amplitude and high frequency signal

An Exclusive-OR logic gate with four two-by-two complementary inputs and two complementary outputs. The structure of this Exclusive-Or gate is said to be symmetrical in that the gate has a propagation time that is identical whichever of the two pairs of complementary inputs is switched over, whatever the nature of the transition at output and whatever the logic state of the pair of inputs that do not switch over. The disclosed device enables a further reduction in the differences in the time taken for the propagation of the signal edges through the gate by eliminating the floating character of certain nodes. It also relates to a frequency multiplier comprising a tree of Exclusive-Or gates such as this.

Exclusive-or logic gate with four two-by-two complementary inputs and

An integrated circuit comprises at least one differential input stage. The differential input stage includes an input circuit and a shaping circuit. The input circuit comprises a first portion and a second portion for providing two pairs of differential signals. The propagation times of the first and second circuit portions are preferably substantially identical. The shaping circuit differentiates each of the two pairs of differential signals and combines them to obtain a single binary type of signal.

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Grenoble, France

Pascal Couteaux