International Business Machines Corporation

X-fab France

X-fab Semiconductor Foundries Ag

Pascal Costaganna

Francis Domart

Philippe Coronel

Pierre De Person

Michel Aube

Nicolas Pons

Lars Heineck

Philippe Trovati

Corentin Boulo

Gregory U'Ren

A transistor carried by a substrate comprising an active layer, the transistor comprising: at least one source area and at least one drain area; at least one electrical contact area; at least one conduction channel; at least one gate; wherein the gate comprises: a longitudinal portion; a transverse portion extending on either side of a portion of the active layer and comprising: at least a first portion extending beyond a portion of a first side of the portion of the active layer on a first extension dimension I; at least a second portion extending beyond a portion of a second side of the portion of the active layer on a second extension dimension I; and in that: I&#x3e;Iwith I&#x2260;0.

Transistor and its manufacturing process

A method for forming an electronic device comprising a first transistor and a second transistor, from a stack of layers comprising an isolating layer surmounted on an active layer made of a semi-conductive material, the method comprising at least the following steps: Forming an isolating trench to define, in the active layer, at least one first active region and at least one second active region, said isolating trench protruding with respect to the active layer of the second active region; Forming a masking layer without covering the active layer of the second active region and without covering a portion of the isolating trench; Etching: of a portion of the thickness of the active layer of the second active region, and of at least one portion of the thickness of said portion of the isolating trench.

Method for forming a microelectronic device

The present invention relates to a method for forming an electronic device intended to accommodate at least one fully depleted transistor of the FDSOI type and at least one partially depleted transistor of the PDSOI type, from a stack of layers () comprising at least one insulating layer () topped with at least one active layer () made of a semiconductor material, the method comprising at least one step of dry etching and one step of height adjustment between at least two etched elements.

Method for the formation of transistors PDSO1 and FDSO1 on a same substrate

According to the disclosed method, there is provided a structure consisting of a silicon substrate coated with a bottom thin SiO2 layer, a doped polysilicon layer, a refractory metal layer and a top Si3N4 capping layer. Said refractory metal and doped polysilicon layers will form a polycide layer under subsequent thermal treatments. First, a sacrificial layer of a dielectric material such as oxynitride is deposited onto the structure. Oxynitride is impervious to UV radiation and has excellent conformal properties. Then, a layer of a photoresist material is deposited onto the structure and patterned to form a mask. Now the dielectric and top Si3N4 layers are anisotropically etched using the photoresist mask. The mask is stripped and the refractory metal and doped polysilicon layers are anisotropically dry etched down to the SiO2 layer using the patterned dielectric layer as an in-situ hard mask. A conformal layer of Si3N4 is deposited onto the structure, then anisotropically dry etched until the thin SiO2 layer is exposed to form the Si3N4 spacers. Diffusion regions are formed in the substrate by ion implantation. A layer of BPSG is deposited onto the structure and planarized. Contact holes are formed to expose said diffusion regions and filled with a metal to create borderless metal contacts therewith.

Method of fabricating a Si3N4/polycide structure using a dielectric sacrificial layer as a mask

A method of plasma etching a Si3N4 masked tungsten silicide layer down to an underlying doped polysilicon layer in the gate conductor stack formation process is disclosed. The method is performed in a plasma etcher and the etching mixture contains C12, HCl and O2 wherein the C12/HCl ratio is approximately equal to 4.7 and the oxygen flow varies between 20 and 30 sccm, 25 sccm being the optimal value. A slight overetching of the underlying doped polysilicon layer with this mixture is recommended. The etching method of the present invention preserves the thickness and integrity of the top Si3N4 masking layer that are essential elements for the successful completion of the remaining steps of the gate conductor stack formation process.

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Chailly en Biere, France

Pascal Costaganna