Texas Instruments Corporation

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Texas Instruments France

Pascal Audinot

Angel Ezquerra-Moreu

Abdellatif Bellaouar

Paul H Fontaine

Andrew M Henwood

Ahmed N Mohieldin

Vincent Roussel

Mikael Guenais

A receiverhas an adjustable gain control circuitthat provides gain control base on the magnitude of the signal at the input of an analog-to-digital converter. The magnitude of a gain increase or decrease can be based on the most significant bits of the analog-to-digital output, indicating whether the analog-to-digital converter is close to saturation, approaching saturation, or well below saturation.

Telecommunications receiver with automatic gain control

A multi-band RF transceiver () includes a single dual band VCO () that is used in both transmit and receive modes of operation. The VCO's low band frequency output signal that is provided on output line () is multiplied by two by multiplier circuit (), when in the high band receive mode, as for example, when receiving a PCS or DCS signal. The VCO's high band frequency output signal provided on output line () is divided by two by divider circuit () when in the low band receive mode, as for example, when receiving a GSM signal. The single multi-band VCO () design provides for low susceptibility to both LO leakage and DC offset caused by radiation.

Method and apparatus for providing a local oscillator signal

A receiveris provided. The receivercomprises an in-phase analog-to-digital converteroperable to detect a saturation condition of the in-phase analog-to-digital converterand to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converterto remove the in-phase analog-to-digital converterfrom the saturation condition and a in-phase digital filteroperable to adjust a gain applied to a digital input to the in-phase digital filterfrom the in-phase analog-to-digital converter, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter. In an embodiment, the receiveralso comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver. In an embodiment, the in-phase analog-to-digital converterand the in-phase digital filtercomprise an intermediate frequency receiver.

Digital detection of blockers for wireless receiver

A method for estimating and removing a time varying DC-offset includes the steps of dividing the received burst into blocks (), then finding the maximum and minimum values in each block (). Once the maximums and minimum values have been found, the upper and lower envelopes are determined (). The DC-offset path is then calculated by taking the average of the upper and lower envelope (). Once determined, the DC-offset path information is used in order to subtract the DC-offset from the desired signal.

Method for estimating and removing a time-varying DC-offset

A method for refining a DC-Offset estimate and removing of the DC-Offset includes the step of determining if any AM is present (). If AM is determined to be present, it is next determined if the I and Q path DC-Offset estimates are closely matched, if they are, then only a single search using the average of the I and Q path estimates is used (). If it determined however, that the two path estimates are not closely matched, than two searches are performed, one for each path (). After this, the blocking signals are searched for up to a predetermined number and the DC-Offset vector is generated (). Once the DC-Offset vector is generated, the DC-Offset is removed from the received signal (). After which it is determined if the AM level is high (), and if so, a transient correction routine is performed ().

Method for refining a DC-offset estimate and removing the DC-offset

A first and second phase-locked loop each having their frequency of operation under programmable control by changing the divider ratio. A single programming word contains the divider ratio for the first phase-locked loop and addressing bits which address a plurality of auxiliary registers for changing the divider ratio of the second phase-locked loop. In a cellular telephone, this allows the digital signal processor to change from receive to transmit mode or from one transmit mode or from one frequency to another utilizing a single command word.

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Valbonne, France

Pascal Audinot