Via Alliance Semiconductor Co., Ltd.

Shanghai Zhaoxin Semiconductor Co., Ltd.

Parviz Palangpour

G Glenn Henry

Kim C Houck

Douglas Raye Reed

Glenn G Henry

A hardware processing unit is provided. The hardware processing unit includes: an accumulator; a multiplier-adder receives first and second factors and receives an addend, the multiplier-adder generates a sum of the addend and a product of the first and second factors and provides the sum; a first multiplexer receives a first operand, a positive one, and a negative one and selects one of them for provision as the first factor to the multiplier-adder; a second multiplexer receives a second operand, a positive one, and a negative one and selects one of them for provision as the second factor to the multiplier-adder; a third multiplexer, having an output, that receives the first operand and the second operand and selects one of them for provision on its output; and a fourth multiplexer receives the third multiplexer output and the sum and selects one of them for provision to the accumulator.

Neural network unit

A memory holds D rows of N words and receives an address having logD bits and an extra bit. Each of N processing units (PU) of index J has first and second registers, an accumulator, an arithmetic unit that performs an operation thereon to accumulate a result, and multiplexing logic receiving memory word J, and for PUs 0 to (N/2)&#x2212;1 also memory word J+(N/2). In a first mode, the multiplexing logic of PUs 0 to N&#x2212;1 selects word J to output to the first register. In a second mode: when the extra bit is a zero, the multiplexing logic of PUs 0 to (N/2)&#x2212;1 selects word J to output to the first register, and when the extra bit is a one, the multiplexing logic of PUs 0 through (N/2)&#x2212;1 selects word J+(N/2) to output to the first register.

Neural network unit with re-shapeable memory

First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J&#x2212;1 and outputs a selected data word to the register. PU J&#x2212;1 for PU 0 is PU N&#x2212;1. The multiplexing logic of PU N/4 also receives the data word output by the register of PU (3N/4)&#x2212;1. The multiplexing logic of PU 3N/4 also receives the data word output by the register of PU (N/4)&#x2212;1.

Neural network unit with segmentable array width rotator

First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J&#x2212;1 and outputs a selected data word to the register. PU J&#x2212;1 for PU 0 is PU N&#x2212;1. The multiplexing logic of PU 0 also receives the data word output by the register of PU (N/2)&#x2212;1. The multiplexing logic of PU N/2 also receives the data word output by the register of PU N&#x2212;1.

First/second memories hold rows of N weight/data words. The first memory address has logW bits and an extra bit. Each of N processing units (PU) of index J has first and second registers, an accumulator, an arithmetic unit performs an operation thereon to accumulate a result, first multiplexing logic for PUsthrough (N/2)&#x2212;1 receives first memory weight words J and J+(N/2) and for PUs N/2 through N&#x2212;1 receives first memory weight words J and J&#x2212;(N/2) and outputs a selected weight word to the first register, and second multiplexing logic receives second memory data word J and data word output by the second register of PU J&#x2212;1 and outputs a selected data word to the second register. PUsecond multiplexing logic also receives PU (N/2)&#x2212;1 second register data word, and PU N/2 second multiplexing logic also receives PU N&#x2212;1 second register data word.

Neural network unit with segmentable array width rotator and re-shapeable weight memory to match segment width to provide common weights to multiple rotator segments

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Austin, TX, United States of America

Parviz Palangpour