Silicon Storage Technology, Inc.

Parviz Ghazavi

Nhan Do

Jinho Kim

Xian Liu

Hieu Van Tran

Feng Zhou

Steven Lemke

Catherine Decobert

Yuri Tkachev

Bruno Villard

Gilles Festes

Bernard Bertello

Henry A Om'Mani

Elizabeth Cuevas

Jean Francois Thiery

Chien-Sheng Su

Prateep Tuntasood

Kai Man Yue

Serguei Jourba

Qing Rao

Ning Bai

Shiuh-Luen Wang

Louisa Schneider

Fan Luo

Cynthia Fung

Latt Tee

A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

Memory cell array with row direction gap between erase gate lines and dummy floating gates

A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RCfor the memory cells and a first number Nof the memory cells having the lowest read current RC. A second read operation is performed to determine a second number Nof the memory cells having a read current not exceeding a target read current RC. The target read current RCis equal to the lowest read current RCplus a predetermined current value. The die is determined to be acceptable if the second number Nis determined to exceed the first number Nplus a predetermined number. The die is determined to be defective if the second number Nis determined not to exceed the first number Nplus the predetermined number.

Method of determining defective die containing non-volatile memory cells

A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

Method of forming split gate memory cells with thinned side edge tunnel oxide

A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

Method of making embedded memory device with silicon-on-insulator substrate

A method of forming a memory device includes forming a floating gate on a memory cell area of a semiconductor substrate, having an upper surface terminating in an edge. An oxide layer is formed having first and second portions extending along the logic and memory cell regions of the substrate surface, respectively, and a third portion extending along the floating gate edge. A non-conformal layer is formed having a first, second and third portions covering the oxide layer first, second and third portions, respectively. An etch removes the non-conformal layer third portion, and thins but does not entirely remove the non-conformal layer first and second portions. An etch reduces the thickness of the oxide layer third portion. After removing the non-conformal layer first and second portions, a control gate is formed on the oxide layer second portion and a logic gate is formed on the oxide layer first portion.

Method of forming split gate memory cells with thinned tunnel oxide

A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.

Method of forming memory array and logic devices

The present invention relates to a flash memory device that uses dummy memory cells as source line pull down circuits. In one embodiment, when a memory cell is in read mode or erase mode, its source line is coupled to ground through a bitline of a dummy memory cell, which in turn is coupled to ground. When the memory cell is in program mode, the bitline of the dummy memory cell is coupled to an inhibit voltage, which places the dummy memory cell in a program inhibit mode that maintains the dummy memory cell in erased state.

Flash memory system using memory cell as source line pull down circuit

An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.

Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates

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San Jose, CA, United States of America

Parviz Ghazavi