Cadence Design Systems, Inc.

Parveen Khurana

Nandu Kumar Chowdhury

Vassilios Constantinos Gerousis

Sachin Shrivastava

Xin Gu

Hongliang Chang

Lizheng Zhang

Yue-Zhong Shu

Babita C Verma

Rishab Dhawan

Sanjeev Azad

Yoshimi Kitagawa

The present embodiments relate to electrostatic discharge (ESD) simulation of integrated circuit designs. A netlist of the circuit design can be modified to include ESD protection devices and only essential non-ESD devices. The essential non-ESD devices can be determined based on whether a non-ESD device satisfies one or more of two conditions: (i) a least resistance path (LRP) value of at least one terminal of the non-ESD device from any port of the set of ports is less than a first threshold value or (ii) an effective resistance value between at least one terminal of the non-ESD device from any port of the set of ports is less than a second threshold value. The essential non-ESD devices are included in a reduced netlist in addition to the ESD protection devices. The ESD simulation is carried out on the reduced netlist, thereby reducing simulation time.

Circuit modification for efficient electro-static discharge analysis of integrated circuits

Disclosed herein are embodiments of systems, methods, and products to automatically and intelligently generate a test bench to test an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) design. A computer may receive netlist of the IC design forming a device under test (DUT). From the DUT, the computer may extract and/or calculate one or more parameters. Based on the one or more parameters, the computer may generate a test bench comprising a resistance inductance capacitance (RLC) circuit to provide ESD stimulus to the DUT. The ESD stimulus and therefore the test bench may be based on a human body model (HBD) or a charged device model (CDM). In case of the CDM, the computer may allow a circuit designer to select or deselect package parameters for testing the ESD protection circuit.

Systems and methods to generate a test bench for electrostatic discharge analysis of an integrated circuit design

Disclosed herein are systems and methods to perform electrical analysis of a circuit design to verify electrical behavior and performance of the circuit design in a two-step process. Initially, a simulator transient analysis is performed on circuit blocks of a circuit design to obtain a current through each device path in each circuit block, and using the current obtained the IR drop and EM problems are examined to get EM-IR drop analysis. Next, a simulator transient analysis is performed on a top level circuit of a circuit design and current values generated in a first step to obtain EM-IR drop analysis for a full circuit design such that a circuit designer may debug, analyze and visualize various IR and EM value plots for circuit blocks and top level circuit of the circuit design together or separately.

Systems and methods for performing electromigration and voltage drop verification in electronic circuit designs

A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of state correlation.

Method and system for performing statistical leakage characterization, analysis, and modeling

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Delhi, India

Parveen Khurana