Western Digital Technologies, Inc.

Rtconfidence, Inc.

Parvaneh Alavi

Haining Liu

Yun-Tzuo Lai

Kai-Lung Cheng

Jerry Lo

Hung-min Chang

Hung-Cheng Yeh

Thomas Cocotis

David Maeschen

Michael M Bissonette

Craig Trivelpiece

A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.

Error recovery handling

A software-based product development portfolio management system and method that may be implemented using a software as a service (SaaS) model that allows users (based on access rights) to: create and update valid project plans using integrated management tools and techniques, view near-real-time project data and metrics; enable lean project management; send messages to other users via system alerts and/or e-mails and receive messages/alerts from other SPM System users; input data; establish and change organizational governance guidelines; and approve, conditionally approve or reject decisions.

Software portfolio management system and method

Aspects of the disclosure provide methods and apparatus that monitor and mitigate Read Disturb errors in non-volatile memory (NVM) devices such as NAND flash memories. The disclosed methods and apparatus determine which logical block addresses (LBAs) in the NVM device are frequently accessed by a host, rather than looking a physical address accesses. The potential Read Disturb errors may then be mitigated by triggering Read Disturb mitigation when the numbers of access of one or more of the frequently accessed LBAs exceeds a predefined number of accesses.

Methods and apparatus for read disturb detection based on logical domain

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Irvine, CA, United States of America

Parvaneh Alavi