Intel Corporation

Parthasarathy Sarangam

Anjali Singhai Jain

Linden Cornett

Manasi Deval

Anil Vasudevan

Rajesh M Sankaran

Sujoy Sen

Nrupal R Jani

Mitu Aggarwal

Kiran A Patil

Kun Tian

Sanjay Kumar

Utkarsh Y Kakaiya

Philip R Lantz

Neerav Parikh

Jesse C Brandeburg

Yadong Li

Ashok Raj

Robert O Sharp

Pratik M Marolia

Donald Wood

Peter P Waskiewicz, Jr

Gregory J Bowers

Mitchell A Williams

Patrick L Connor

Daniel Todd Cohn

Mrittika Ganguli

Eric K Mann

Ronen Chayat

Joshua A Hay

Kevin C Scott

Alexander H Duyck

Donald Skidmore

David M Durham

Ravi L Sahita

Arvind Srinivasan

Raj K Ramanujan

Jr-Shian Tsai

Susanne M Balle

Ben-Zion Friedman

Scott P Dubal

Eliel Louzoun

Stephen T Palermo

Steven R King

Frank L Berry

Ilango S Ganga

Iosif Gasparakis

Andrey Chilikin

Arun Raghunath

D Michael Bell

Cunming Liang

Ramakrishna Huggahalli

Alain Gravel

Trevor Cooper

Noam Elati

Chih-Jen Chang

Ygdal Naouri

Shaopeng He

Naru Dames Sundar

Pradeepsunder Ganesh

Malek Musleh

Elazar Cohen

Sugesh Chandran

Haitao Kang

Mike Bursell

Padma Akkiraju

Shaul Yifrach

Alexander Nguyen

Sunil Ahluwalia

Sanjay K Kumar

Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file. Other embodiments are described and claimed.

Technologies for programming flexible accelerated network pipeline using EBPF

Technologies for accelerated HTTP message processing include a computing device having a network controller. The computing device may generate an HTTP message, frame the HTTP message to generate a transport protocol packet such as a TCP/IP packet or QUIC packet, and pass the transport protocol packet to the network controller. The network controller compresses the HTTP header of the HTTP message, encrypts the compressed HTTP message, and transmits the encrypted message to a remote device. The network controller may segment the transport protocol packet into multiple segmented packets. The network controller may receive transport protocol packets that include encrypted HTTP message. The network controller decrypts the encrypted HTTP message to generate a compressed HTTP message, decompresses the HTTP message, and steers the HTTP message to a receive queue based on contents of an HTTP header. The network controller may coalesce multiple transport protocol packets. Other embodiments are described and claimed.

Technologies for accelerated HTTP processing with hardware acceleration

A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

Network interface for data transport in heterogeneous computing environments

Examples described herein relate to a switch configured to allocate packet processing resources, from a pool of packet processing resources, to multiple applications, wherein the pool of packet processing resources comprise configurable packet processing pipelines of one or more network devices and packet processing resources of one or more servers. In some examples, the configurable packet processing pipelines and the packet processing resources are to perform one or more of: network switch operations, microservice communications, and/or block storage operations. In some examples, the network switch operations comprise one or more of: application of at least one access control list (ACL), packet forwarding, packet routing, and/or Virtual Extensible LAN (VXLAN) or GENEVE termination. In some examples, the microservice communications comprise one or more of: packet routing between microservices and/or load balancing of utilized microservices.

Pooling of network processing resources

Flexible schemes for adding rules to a NIC pipeline and associated apparatus. Multiple match-action tables are implemented in host memory of a platform defining actions to be taken for matching packet flows. A packet processing pipeline and an exact match (EM) cache is implemented on a network interface, such as a NIC, installed in the platform. A portion of the match-action entries in the host memory match-action tables are cached in the EM cache. Received packets are processed to generate a key that is used as a lookup for the EM cache. If a match is found, the action is taken. For a miss, the key is forwarded to the host software and the match-action tables are searched. For a match, the action is taken, and the entry is added to the EM cache. If no match is found, a new match-action entry is added to a match-action table. Aging-out mechanisms are used for the match-action tables and the EM cache. A multi-hash scheme is used to that supports a very large number of match-action entries.

Flexible scheme for adding rules to a NIC pipeline

Examples may include a method of instantiating a virtual machine, instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the virtual device.

Virtual device composition in a scalable input/output (I/O) virtualization (S-IOV) architecture

Techniques for providing adaptive virtual function (VF) drivers capable of operating with physical devices having a plurality of different hardware configurations are described. In one embodiment, for example, an apparatus may include logic to implement a virtual machine (VM), the logic to initialize an adaptive virtual function (VF) driver to facilitate communication between the VM and a physical device to be virtualized, establish communication between the adaptive VF driver and a physical function (PF) driver of the hypervisor for the physical device, activate a standard feature set for the adaptive VF driver to execute on a PF of the physical device, and negotiate activation of an advanced feature set for the adaptive VF driver to execute on the PF, the adaptive VF driver to provide the advanced feature set to the PF, the PF activate each feature of the advanced feature set supported by the PF.

Adaptive virtual function drivers for electronic devices

Packets received non-contiguously from a network are processed by a network interface controller by coalescing received packet payload into receive buffers on a receive buffer queue and writing descriptors associated with the receive buffers for a same flow consecutively in a receive completion queue. System performance is optimized by reusing a small working set of provisioned receive buffers to minimize the memory footprint of memory allocated to store packet data. The remainder of the provisioned buffers are in an overflow queue and can be assigned to the network interface controller if the small working set of receive buffers is not sufficient to keep up with the received packet rate. The receive buffer queue can be refilled based on either timers or when the number of buffers in the receive buffer queue is below a configurable low watermark.

Apparatus and method for buffer management for receive segment coalescing

Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located. After asserting an interrupt, an RX queue may be auto-masked to prevent generation of additional events when new descriptors are enqueued in the RX queue.

Efficient receive interrupt signaling

Technologies for programming flexible accelerated network pipeline using eBPF

Methods, apparatus, and systems for data plane interface network Quality of Service (QoS) in multi-tenant data centers. Data plane operations including packet generation and encapsulation are performed in software running in virtual machines (VMs) or containers hosted by a compute platform. Control plane operations, including QoS traffic classification, are implemented in hardware by a network controller. Work submission and work completion queues are implemented in software for each VM or container. Work elements (WEs) defining work to be completed by the network controller are generated by software and processed by the network controller to classify packets associated with the WEs into QoS traffic classes, wherein packets belonging to a give traffic flow are classified to the same QoS traffic class. The network controller is also configured to perform scheduling of packet egress as a function of the packet's QoS traffic classifications, to transmit packets that are scheduled for egress onto the network, and to DMA indicia to the work completion queues to indicate the work associated with WEs has been completed.

Data plane interface network quality of service in multi-tenant data centers

Examples described herein can be used to allocate replacement receive buffers for use by a network interface, switch, or accelerator. Multiple refill queues can be used to receive identifications of available receive buffers. A refill processor can select one or more identifications from a refill queue and allocate the identifications to a buffer queue. None of the refill queues is locked from receiving identifications of available receive buffers but merely one of the refill buffers is accessed at a time to provide identifications of available receive buffers. Identifications of available receive buffers from the buffer queue are provide to the network interface, switch, or accelerator to store content of received packets.

Receive buffer management

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Portland, OR, United States of America

Parthasarathy Sarangam