Gm Global Technolgoy Operations, Inc.

Synopsys, Inc.

Indian Institute of Technology Kharagpur

Partha Pratim Chakrabarti

Dipankar Das

Kaushik De

Eduard Rudolf Cerny

Bhaskar Pal

Pallab Dasgupta

Purnendu Sinha

An apparatus and method are provided for analyzing fault tolerance of a system, and performing 'what if?' analysis for various fault-tolerant system design options. The fault tolerance analysis approach handles logical failures and quality faults emanating from loss of precision in signal values. The method can detect quality faults, which can allow systems to be built which are resilient to precision losses. Two analysis steps are provided, one static and another simulation-based, which are used in tandem to check the fault tolerance of an automotive or other system. While a simulation-based method checks fault-resilience under specific test cases and fault-scenarios, the static analysis method quickly checks all test cases and fault-scenarios. The static analysis method makes approximations while performing the analysis, and any fault detected is reproduced using the simulation-based method. All analysis operations are performed on operations-level behavioral models of the applications, thereby reducing the cost of analysis.

Method and apparatus for operational-level functional and degradation fault analysis

One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.

Method and apparatus for extracting assume properties from a constrained random test-bench

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Kharagpur, India

Partha Pratim Chakrabarti