Tokyo Electron Limited

Partha Mukhopadhyay

Mark I Gardner

H Jim Fulford

A semiconductor device includes a memory cell unit positioned over a substrate. The memory cell unit includes a transistor and a capacitor. The capacitor includes an inner conductor, a capacitor dielectric all around the inner conductor, an outer conductor all around the capacitor dielectric, and dielectric support structures below the inner conductor. The capacitor is elongated in a length direction parallel to a working surface of the substrate, and the dielectric support structures are spaced along the length direction. The transistor includes a channel structure, a gate structure all around the channel structure, and source/drain (S/D) regions on opposing ends of the channel structure.

3D horizontal memory cell with sequential 3D vertical stacking

Methods for the manufacture of semiconductor devices constructed with three-dimensional (3D) horizontal nano sheets with high mobility two-dimensional (2D) material channels are disclosed. Aspects can include forming a semiconductor material; selectively forming a seed material around the bridge; selectively forming a two-dimensional (2D) material around the seed material; forming an active gate around a central portion of the 2D material thereby exposing end portions of the 2D material; and growing source/drain structures coupled to the end portions of the 2D material, respectively.

Epitaxial semiconductor 3D horizontal nano sheet with high mobility 2D material channel

A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; selectively depositing an outer spacer layer on the dummy gate structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; and forming a metal gate structure to fill the gate trench and the openings.

Semiconductor devices and methods of manufacturing thereof

Aspects of the present disclosure provide a method for fabricating a semiconductor structure. For example, the method can include forming a stack of metal structures on a substrate, the stack of metal structures including multiple metal structures that are vertically stacked over and electrically separated from one another, each of the metal structures including a ring and one or more pad contacts extending from the ring, the rings of the metal structures being vertically aligned with one another. The method can also include forming one or more channel structures within the rings of the metal structures, the channel structures being electrically separated from one another and electrically separated from the substrate. The method can also include forming one or more interconnections that extend from a position above the stack of metal structures to corresponding one or more of the pad contacts of the metal structures.

Multi-dimensional metal first device layout and circuit design

Vertical transistors and methods of manufacturing vertical transistors are disclosed. The method can include forming a stack of layers include a first layer stack of a first transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material. The stack of layers can include a second layer stack of a second transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material, the second layer stack associated with a second transistor structure. The first and second transistor structures are separated by one or more dielectric materials. The method can include forming a channel opening in the stack. The method includes selectively forming a first channel structure within the channel opening and selectively forming a second channel structure within the channel opening.

Vertical transistor structures and methods utilizing selective formation

Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.

Formation of high density 3D circuits with enhanced 3D conductivity

Methods for the manufacture of semiconductor devices constructed with two-dimensional (2D) materials and conductive oxides using three-dimensional (3D) nanosheets are disclosed. Aspects can include forming the stack of layers comprising a first layer of a semiconductive-behaving material separated from a base layer by a first layer of a first dielectric material and a first layer of a second dielectric material; a second layer of the semiconductive-behaving material separated from the first layer of the semiconductive-behaving material by a second layer of the second dielectric material; and a second layer of the second dielectric material formed on the second layer of the semiconductive-behaving material. Aspects include forming a metal contact coupled with the semiconductive-behaving material, forming a 2D material on the semiconductive-behaving material, forming a layer of a high-k dielectric material on the 2D material, and forming a gate metal on the high-k dielectric material.

3D nano sheet method using 2D material integrated with conductive oxide for high performance devices

Three-dimensional (3D) memory structures and methods to manufacture 3D memory structures are disclosed. A method includes forming a stack of layers including a first sub-stack for a first transistor structure, comprised of a first conductive layer, a gate layer, and a second source/drain layer. The stack of layers can include a second sub-stack for a memory structure positioned on the first sub-stack, the second sub-stack including at least one layer of conductive material and at least one layer of non-conductive material, and a third sub-stack for a second transistor structure. The method includes forming a channel opening in the stack of layers, providing a first channel structure within the channel opening, forming a memory dielectric layer in the channel opening and aligned with the memory structure, and providing a second channel structure in the channel opening in contact with the memory dielectric layer and aligned with the second transistor structure.

3D memory with conductive dielectric channel integrated with logic access transistors

A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

Ultra dense 3D routing for compact 3D designs

Apparatuses, devices, and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

Method of making of plurality of 3D vertical logic elements integrated with 3D memory

Methods for the manufacture of three-dimensional (3D) semiconductor devices are disclosed. Aspects can include forming a patterned first conductive source/drain structure of a transistor structure, forming a gate patterned conductive structure of the transistor structure separated from the first conductive source/drain structure by at least one dielectric layer, forming a patterned second conductive source/drain structure of the transistor structure separated from the gate patterned conductive structure by at least one dielectric layer, forming a transistor body opening extending through the transistor structure, forming a gate dielectric in the transistor body opening, and forming a material in the transistor body opening extending from the patterned first conductive source/drain structure to the patterned second conductive source/drain structure.

3D high density compact metal first approach for hybrid transistor designs without using epitaxial growth

Apparatuses, devices and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

3D stacked DRAM with 3D vertical circuit design

According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of insulating layers and interconnect layers that are positioned alternatingly over a substrate. The semiconductor device includes a channel structure extending from the substrate and further through the insulating layers and the interconnect layers. The channel structure includes a first channel section positioned over the substrate and coupled to a first group of the interconnect layers, and a second channel section positioned over the first channel section and coupled to a second group of the interconnect layers. The semiconductor device also includes a plurality of contact structures extending from and coupled to the interconnect layers in a staircase configuration such that each of the plurality of contact structures extends from a respective interconnect layer.

Three-dimensional device with self-aligned vertical interconnection

Aspects of the present disclosure provide a method for forming a semiconductor structure having separated vertical channel structures. The method can include forming a layer stack on a substrate, the layer stack including alternating metal layers and dielectric layers. The method can further include forming vertically stacked lower and upper vertical channel structures vertically extending through the layer stack, the lower and upper vertical channel structures being separated by a sacrificial layer. The method can further include forming source, drain and gate connections to the lower and upper vertical channel structures, the source, drain and gate connections extending horizontally from the lower and upper vertical channel structures and then vertically to a location above the upper vertical channel structure. The method can further include forming a vertical opening in the layer stack and removing the sacrificial layer through the vertical opening to separate the lower and upper vertical channel structures.

Growing community of inventors

Oviedo, FL, United States of America

Partha Mukhopadhyay