Inphi Corporation

Marvell Asia Pte., Ltd.

Parmanand Mishra

Simon D Forey

Rajasekhar Nagulapalli

Michael Stephen Harwood

Steffen O Nielsen

Sean Batty

Karthik S Gopalakrishnan

Guojun Ren

Richard J Ward

Karthik Raviprakash

Yida Duan

The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.

Clock data recovery circuit including charge pump having reduced glitch current

The present invention is directed to communication systems and electrical circuits. According to an embodiment, the present invention provides a termination circuit that includes an inductor network. The inductor network is coupled to a termination resistor and a capacitor network, which includes a first capacitor and a second capacitor. The termination resistor, the first capacitor, and the second capacitor are adjustable, and they affect attenuation of the termination circuit. There are other embodiments as well.

Termination circuits and attenuation methods thereof

High-speed linear charge pump circuits for clock data recovery

The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.

Charge pump circuits for clock and data recovery

The present invention is directed to communication systems and electrical circuits. According to an embodiment, an input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance. There are other embodiments as well.

Input termination circuits for high speed receivers

The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

Variable gain amplifiers for communication systems

The present invention is directed to data communication. In a specific embodiment, a known data segment is received through a data communication link. The received data is equalized by an equalizer using an adjustable equalization parameter. The output of the equalizer is sampled, and a waveform is obtained by sweeping one or more sampler parameters. The waveform is evaluated by comparing it to the known data segment. Based on the quality of the waveform, equalizer parameter is determined. There are other embodiments as well.

Method and system for calibrating equalizers

Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.

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Cupertino, CA, United States of America

Parmanand Mishra