Xilinx, Inc.

Parimal Patel

Patrick Lysaght

Graham F Schelle

Yun Qu

Stephen Andrew Neuendorffer

Peter K Ogden

An integrated circuit can include programmable circuitry configured to implement an overlay circuit specified by an overlay and a processor coupled to the programmable circuitry. The processor can be configured to control the programmable circuitry through execution of a framework. The framework provides high-productivity language control of implementation of the overlay in the programmable circuitry.

Productivity platform using system-on-chip with programmable circuitry

A system includes a runtime generator implemented in programmable circuitry of an integrated circuit, wherein the runtime generator is parameterizable at runtime of the integrated circuit to perform at least one of detecting a symbol pattern within a data stream or generating pseudo random number binary sequences. The system can include a processor configured to execute program code, wherein the processor is configured to provide first parameterization data to the runtime generator. In response to receiving the first parameterization data from the processor at runtime of the integrated circuit, the runtime generator implements a first automaton circuit configured to perform the at least one of the detecting the symbol pattern or the generating the pseudo random number binary sequences.

Runtime generators for regular expression matching and random number generation

An integrated circuit can include programmable circuitry configured to implement an overlay circuit specified by an overlay. The overlay circuit can include a trace buffer configured to receive a probed signal from circuitry within the overlay circuit. The trace buffer can be configured to generate trace data from the probed signal and store the trace data in a runtime allocated memory. The integrated circuit also can include a processor coupled to the programmable circuitry and configured to control operation of the trace buffer. The processor can be configured to read the trace data from the runtime allocated memory.

Hardware trace and introspection for productivity platform using a system-on-chip

An integrated circuit can include a slave processor configured to execute instructions. The slave processor can be implemented in programmable circuitry of the integrated circuit. The integrated circuit also can include a processor coupled to the slave processor. The processor can be hardwired and configured to control operation of the slave processor.

Slave processor within a system-on-chip

A system can include a finite state machine generator implemented in programmable circuitry of an integrated circuit. The finite state machine generator is parameterizable to implement different finite state machines at runtime of the integrated circuit. The system can include a processor configured to execute program code. The processor is configured to provide first parameterization data to the finite state machine generator at runtime of the integrated circuit. The first parameterization data specifies a first finite state machine and the finite state machine generator implements the first finite state machine in response to receiving the first parameterization data from the processor.

Runtime adaptive generator circuit

A method for configuring programmable logic in an IC to implement instances of a relocatable circuit includes, for each instance, assigning a respective portion of an address space of a processor to the instance, configuring a respective interface circuit for translating the transactions accessing the respective portion of the address space into a fixed address space of the relocatable circuit, and selecting a respective region within an array of programmable logic and interconnect resources of the IC. The processor accesses the address space with read and write transactions issued on an interface bus. The relocatable circuit is independent of the address space assigned to the instances. Each region is configurable to implement an instance. The programmable logic and interconnect resources are configured to implement the instances and to couple each instance to the interface bus of the processor via the respective interface circuit, using a single copy of configuration data for the relocatable circuit.

Methods of implementing relocatable circuits in a programmable integrated circuit device

A circuit is implemented using a programmable logic device (PLD) that includes an array of programmable logic and routing resources. The circuit includes a processor, a configuration port, a relocatable circuit, and an interface circuit. The processor accesses an address space using read and write transactions issued on an interface bus. The programmable logic and interconnect resources are configurable via the configuration port. The relocatable circuit is implemented in a selected region within the array by configuring the programmable logic and interconnect resources in the selected region with configuration data via the configuration port. The interface circuit translates the transactions accessing a portion of the address space assigned to the relocatable circuit into a fixed address space of the relocatable circuit. The configuration data for implementing the relocatable circuit is independent of the portion of the address space assigned to the relocatable circuit.

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San Antonio, TX, United States of America

Parimal Patel