Synopsys, Inc.

Parijat Biswas

Sitikant Sahu

Minakshi Chakravorty

Pravash Chandra Dash

Alexander John Wakefield

Alexandru Seibulescu

Raghurama Krishna Srigiriraju

Sharad Nijhawan

Ractim Chakraborty

Manoharan Vellingiri

Shyam Datta

Danish Jawed

Subhrajyoti Chakraborty

Rajarshi Mukherjee

Rahul Garg

Jiang Chen

Ying Chen

Bhaskar Pal

Gagan Vishal Jain

Badri P Gopalan

Esha Dutta

Sharad Gaur

Jayant Nagda

Enzhi Ni

A method for verifying an integrated circuit (IC) design described in a hardware description or hardware verification language (HDHVL) is provided. The method includes identifying connections between random variables and coverage areas of the IC design, as described in HDHVL code, the connections being identified by determining which coverage areas of the IC design will be influenced during simulation by which random variables. The method can further include storing the identified connections in a database, and using, by a processor, connections retrieved from the database to simulate and verify the coverage areas of the IC design.

Connecting random variables to coverage targets using an ensemble of static analysis, dynamic analysis and machine learning and guided constraint solving of the random variables during simulation of an integrated circuit

Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be transformed based on the second pattern to obtain a transformed portion of the HDL code. The portion of the HDL code may be replaced by the transformed portion of the HDL code.

Performing hardware description language transformations

Hardware simulation systems and methods for reducing signal dumping time and size of by fast dynamical partial aliasing of signals having similar waveform are provided. One example system is configured to receive, in real-time, a first signal from a producer entity; determine a first signal signature associated with the first signal; determine, in real-time, a second signal signature associated with the second signal; upon determining that the first signal signature matches the second signal signature, designate the first signal as a master signal and designate the second signal as a slave signal; and stop dumping the second signal to a storage space.

Hardware simulation systems and methods for reducing signal dumping time and size by fast dynamical partial aliasing of signals having similar waveform

A data analysis engine is implemented in a testbench to improve coverage convergence during simulation of a device-under-validation (DUV). During a first simulation phase initial stimulus data is generated according to initial random variables based on user-provided constraint parameters. The data analysis engine then uses a time-based technique to match coverage variables sampled from simulation response data with corresponding initial random variables, determines a functional dependency (relationship) between the sampled coverage variables and corresponding initial random variables, then automatically generates revised constraint parameters based on the functional dependency. The revised constraint parameters are then used during a second simulation phase to generate focused random variables used to stimulate the DUV to reach additional coverage variables. In one embodiment, the functional dependency is determined by cross-correlating sampled coverage variables and corresponding initial random variables.

Automated coverage convergence by correlating random variables with coverage variables sampled from simulation result data

The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in the same horizontal or vertical region, to give the user an intuitive view of time going left to right or top to bottom.

Graphical view and debug for coverage-point negative hint

A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises determining a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after a timestamp depending on the input signal and/or on the value of the output signal directly before the timestamp. The method further comprises computing the value of the at least one output signal directly after the timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.

Signal reconstruction in sequential logic circuitry

A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after the simulation timestamp depending on the input signal and/or on the value of the output signal directly before the simulation timestamp. The method further comprises computing the value of the at least one output signal directly after the simulation timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.

In a method for increasing coverage convergence during verification of a design for an IC, symbolic elements can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Simulation semantics can be modified and local multi-path analysis can be provided to expand symbolic property collection and symbolic element propagation. Modifying simulation semantics can include transformation of conditional statements, flattening of conditions, avoidance of short circuiting logic, and/or symbolic triggering of events. Symbolic elements are propagated through the design and the test bench during multiple simulation runs to collect symbolic properties. Coverage information from the multiple simulation runs is analyzed to identify coverage points to be targeted. For each identified coverage point, the constraints resulting from the collected symbolic properties are solved to generate directed stimuli for the design. These directed stimuli increase the coverage convergence.

Accelerating coverage convergence and debug using symbolic properties and local multi-path analysis

In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Exemplary hardware code can include the hardware description language (HDL) code and/or the hardware verification language (HVL) code. Symbolic properties, which are derived from propagating the symbolic variables and symbolic expressions through the design and the test bench during the multiple simulation runs, can be collected. Coverage information from the multiple simulation runs can be analyzed to identify coverage points to be targeted. At this point, for each identified coverage point, the constraints resulting from the collected symbolic properties can be solved to generate directed stimuli for the design. These directed stimuli can increase the coverage convergence.

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Karnataka, India

Parijat Biswas