Synopsys, Inc.

Atrenta, Inc.

Paras Mal Jain

Maher Mneimneh

Sudeep Mondal

Deepak Ahuja

Rajarshi Mukherjee

Mohammad Homayoun Movahed-Ezazi

Mohamed Shaker Sarwary

Namit Gupta

Shaker Sarwary

Anchit Jain

Ashish Bansal

Anshu Malani

Kaushik De

David L Allen

Brijesh Agrawal

Barsneya Chakrabarti

Fahim Rahim

Abhishek Verma

Abhinav Singla

Deep Shah

Dipit Ranjan Senapati

Abhishek Kumar

Satrajit Pal

Anshul Tuteja

Scott Cotton

Ankit Arora

Pronay Kumar Biswas

A method of performing static verification of a circuit design that includes a number of circuit blocks, includes, in part, receiving a first model of a first block generated using a first version of a verification tool and having associated therewith data representative of a version number of each of a multitude of verification tests performed by the first version of the tool as well as associated first setup information. In response to the determination that, for each of the of tests performed, the version number of the test to be run on the circuit design is incompatible with the version number of the test performed by the first version of the tool, portions of the first model that were tested with the version number(s) of the test(s) determined to be incompatible with the version number(s) of the test(s) to be run on the circuit design are regenerated.

Multi-machine version independent hierarchical verification

A method includes: receiving an integrated circuit design; classifying, by the processing device, a signal path of a sub-circuit of the integrated circuit design based on a connection between an input port of the signal path and a component of the sub-circuit to generate a classification of the signal path; computing, by the processing device, a security vulnerability result of the sub-circuit of the integrated circuit design based on the classification of the signal path and based on a trust level of a zone in a fan-in cone to an input port of the signal path; and generating a security vulnerability report based on the security vulnerability result of the sub-circuit of the integrated circuit design.

Hardware security checks in static verification of integrated circuit designs

Sets of objects may be received which are desired to be stored using a nested hash map, where the nested hash map may include multiple levels, and where each set of objects in the sets of objects may correspond to a level in the nested hash map. The nested hash map may be created from a bottom level of the nested hash map to a top level of the nested hash map, which may include: creating a first hash map at a first level of the nested hash map, creating a first shared pointer which points to the first hash map, and creating a second hash map at a second level which is immediately above the first level, where the second hash map maps at least one object to the first shared pointer.

Memory optimization for storing objects in nested hash maps used in electronic design automation systems

Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation point.

Reset domain crossing detection and simulation

Disclosed herein are system, computer-readable storage medium, and method embodiments of machine-learning (ML)-based static verification for derived hardware-design elements. A system including at least one processor may be configured to extract a feature set from a hardware description and evaluate a similarity index of a first hardware element with respect to a second hardware element, using an ML process based on the feature set, wherein the first hardware element is described in the hardware description. The at least one processor may be further configured to update one or more parameters corresponding to a static verification of the hardware description while the static verification is being performed, by providing at least one test attribute, corresponding to the second hardware element, applicable to the first hardware element, in response to determining that the similarity index is within a specified range, and additionally output a first result of the static verification.

Machine learning (ML)-based static verification for derived hardware-design elements

A system and method for providing convergence centric coverage for clock domain crossing (CDC) jitter in simulation is described. The method includes, in part, defining one or more design constraints associated with the circuit design, determining at least one group of converging signals associated with the circuit design using the one or more design constraints, applying a multitude of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals, and storing the jitters in a jitter database.

Convergence centric coverage for clock domain crossing (CDC) jitter in simulation

The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.

Determining and verifying metastability in clock domain crossings

A method and a system for identifying glitches in a circuit are provided. The method includes identifying a sub-circuit that drives a net from a plurality of nets in a circuit, generating a glitch detection circuit comprising dual-rail encoding from the net to a signal driver of the sub-circuit, modifying the sub-circuit to include the glitch detection circuit, generating an optimized hardware design language (HDL) output file associated with the glitch detection circuit and the sub-circuit, and performing a simulation or a formal verification of the optimized HDL output file to determine whether a signal associated with the net glitches.

Verifying glitches in reset path using formal verification and simulation

Techniques for verification of integrated circuit design are disclosed. A design relating to an integrated circuit is received (). The design includes a first parameterized element and a second parameterized element (). The first parameterized element is identified as a do-not-care (DNC) element based on usage of the first parameterized element in the design (). A plurality of models relating to the design are generated by a processing device (). A first value of the first parameterized element is not varied during the generating, based on the identification of the first parameterized element as a DNC element (). A second value of the second parameterized element is varied during the generating ().

Clock domain crossing verification of integrated circuit design using parameter inference

A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.

System and method for managing and composing verification engines

A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.

System and method for metastability verification of circuits of an integrated circuit

Clock-domain crossing (CDC) verification for system on chip (SoC) integrated circuits (IC) can be time consuming and complex, especially as the size of the SoC and the complexity of the modules of which it comprises increase. A bottom-up verification process includes the replacement of a CDC verified module by an abstracted model of the module with constraints defined on the boundaries of the module. Performing the process in a hierarchic manner from bottom upwards allows for faster verification of modules higher in the hierarchy as at least portions thereof are replaced with the abstracted modules.

Hierarchical bottom-up clock domain crossing verification

A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.

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Cupertino, CA, United States of America

Paras Mal Jain