Qualcomm Incorporated

Paras Gupta

Parissa Najdesamii

Ramaprasath Vilangudipitchai

Rajesh Verma

Raghavendra Dasegowda

Sundararajan Ranganathan

Alan G Lewis

Martin Saint-Laurent

Nam Dang

Giby Samson

Dorav Kumar

Rajeev Jain

Kamesh Medisetti

Swarna Navubothu

Smeeta Heggond

Mamta Bansal

Keyurkumar Karsanbhai Kansagra

Tung Nang Pham

Kelageri Nagaraj

V Karthik Venkataraman

Uday Doddannagari

Joseph Terregrossa

Nitin Partani

Somasekhar Maradani

Jitu Khushalbhai Mistry

Arshath Sheeparamatti

Aklesh Jain

A system on chip (SOC) comprising: first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexor disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block; and enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to control terminals of the first power multiplexor.

Systems and methods for adaptive power multiplexing

Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.

Differential current sensing with robust path, voltage offset removal and process, voltage, temperature (PVT) tolerance

Methods and apparatuses for efficiently providing supply voltages to a load circuit are provided. The apparatus includes a first plurality of first power buses extending in a first direction and within a first range. The first range extends in a second direction. A second plurality of first power buses extends in the first direction and within the first range. The first plurality of first power buses and the second plurality of first power buses are powered at a first supply voltage. A plurality of second power buses extends in the first direction within the first range and a second range. The second range extends in the first direction. The plurality of second power buses is powered at a second supply voltage. The first plurality of first power buses, the second plurality of first power buses, and the plurality of second power buses are in a conductive layer.

First power buses and second power buses extending in a first direction

A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Multi supply cell arrays for low power designs

A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains

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San Diego, CA, United States of America

Paras Gupta