Synopsys, Inc.

Paras Chhabra

Denis Martin

Amit Gopal M Purohit

Sorin Ioan Popa

A first scan pattern may be received to test a first circuit block in an integrated circuit (IC) design and a second scan pattern may be received to test a second circuit block in the IC design. A first length of the first scan pattern may be different from a second length of the second scan pattern. The first scan pattern, the second scan pattern, or both the first scan pattern and the second scan pattern may be modified to make lengths of the first scan pattern and the second scan pattern equal.

Modifying scan patterns to enable broadcasting a scan enable signal to multiple circuit blocks

A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.

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Bengaluru, India

Paras Chhabra