Hewlett-packard Development Company, L.p.

Paras A Shah

Ryan J Hensley

Prashantha Kalluraya

Phillip M Jones

Kenneth A Jansen

William J Walker

James K Yu

Jaideep Dastidar

Randall John Pascarella

Timothy K Waldrop

Andrew D Olsen

Vasileios Balabanos

A system comprises a plurality of nodes coupled together via a switching device. Each node comprises a processor coupled to a memory. Migration logic in the switching device is configured to migrate segments of each memory to the switching device.

Method and system for migrating memory segments

A bus device comprises a clock generator that is adapted to generate a clock signal for internal use by the bus device, data synchronizing logic that is adapted to synchronize source synchronous data that the bus device receives from the bus to the bus device's clock signal, and error detection and correction logic coupled to the data synchronizing logic. The error detection and correction logic is adapted to detect and correct errors associated with the data received from the bus concurrently while the data synchronizing logic synchronizes source synchronous data received from the bus to the clock signal.

Bus device that concurrently synchronizes source synchronous data while performing error detection and correction

A method and architecture optimizes transaction ordering in a hierarchical bridge environment. A parent-bridge is one level above a child-bridge, which in turn is one level above a grand-child component. The parent-bridge is a bridge-bridge. The child-bridge can be a bus-bridge or a bridge-bridge. The grand-child component can be a bus, a bus-bridge or a bridge-bridge. A parent-bridge is connected to a child-bridge via child-links, the child-bridge connected to grandchild-links, and the parent-bridge having multiple transaction order queues (TOQs) per child-link. Ideally, the parent-bridge has one TOQ for each grandchild-link where the parent-bridge applies separate transaction ordering for each of the grandchild-links. However, at a minimum, the system uses at least two TOQs per child-link, and as such, provides a higher level of transaction throughput than systems using one TOQ per child-link. The child-bridge sends a signal to the parent-bridge identifying from which grandchild-link a transaction was sent.

System to optimally order cycles originating from a single physical link

A technique for an enhanced transaction order queue is disclosed. A transaction order queue is used to prioritize transactions flowing through a bridge. The present technique enhances the transaction order queue by providing logic within a module, facilitating the enqueuing of a plurality of transaction entries within a single device and ensures that PCI/PCI-X ordering rules are not violated. The technique also provides that the logic device within the PCI-X bridges and buses selects and enqueues a single transaction entry from simultaneous multiple transaction entries.

Enhancement of transaction order queue

A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system with multiple nodes in a transaction order queue (TOQ). Interconnect transactions are dequeued from the TOQ and scheduled for a destination node through a buffer between the TOQ and a scheduler. Interconnect transactions of the first transaction type are blocked from the scheduler until all interconnect transactions scheduled for other nodes in the computer system have completed. No interconnect transactions are dequeued from the TOQ while an interconnect transactions of the first transaction type is blocked from the scheduler. The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol.

Method and apparatus for ordering interconnect transactions in a computer system

An application specific integrated circuit (ASIC) employs various logic blocks. The blocks may include logic circuits that operate at different clock rates. Consequently, an interface logic block may be needed to efficiently transfer signals from one frequency clock domain to another. One such interface, known as a universal asynchronous boundary module (UABM) is situated between the two domains allowing communication between the logic circuits.

Universal asynchronous boundary module

A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system in a transaction order queue (TOQ). The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol. Transactions can bypass the TOQ if no transactions of the first type are awaiting execution or are in the TOQ. Transactions are dequeued from the TOQ if no transactions of either the first transaction type or the second transaction type are awaiting scheduling for execution.

A method for processing a PCI-X transaction in a bridge is disclosed, wherein data is retrieved from a memory device and is stored in a bridge then delivered to a requesting device. The method may comprise the acts of allocating a buffer in the bridge for the PCI-X transaction, retrieving data from a memory device, wherein the data comprises a plurality of cachelines, storing the plurality of cachelines in the buffer, wherein the plurality of cachelines are tracked and marked for delivery as the plurality of cachelines are received in the buffer, and delivering the plurality of cachelines to the requesting device in address order, the plurality of cachelines transmitted to the requesting device when one of the plurality of cachelines in the buffer aligns to an ending address of an allowable disconnect boundary (ADB) and the remaining cachelines are in address order.

Enhancing a PCI-X split completion transaction by aligning cachelines with an allowable disconnect boundary's ending address

A technique is provided for prioritizing access to a bus for read completion transactions. The technique incorporates logic within an ASIC bridge, wherein split completion transactions are designated a priority level that facilitates the delivery of the requested data to a periphery device. Particularly, logic within the ASIC grants a read completion transaction a level one priority designation, which provides access to the bus to a requesting device prior to devices designated with a level two priority designation.

Method and system to promote arbitration priority in a buffer queue

A test circuit receives a plurality of internal test signals and delivers a group of the plurality of internal test signals onto a bus during an idle state of the bus. The bus is coupled to output pins so that the group of internal test signals can be used in debugging operations. The test circuit may include a multiplexing circuit that receives the plurality of internal test signals as inputs and that delivers a selected group of the internal test signals as outputs. The test circuit may also include a switch that couples the selected group of the internal test signals onto the bus during an idle state.

Test outputs using an idle bus

A computer system containing logic for processing a read block transaction from a PCI-X device. A technique is also disclosed for processing a read block transaction from a PCI-X device. The technique is defined by PCI-X specifications wherein the read block transaction is processed accordingly in a computer system. The technique determines whether the transaction is a read block and whether the transaction crosses a memory boundary. The technique also determines whether a page roll is required and administers one if it is required. Furthermore, the technique provides a means for reading and delivering the data to a PCI-X device.

Buffer page roll implementation for PCI-X block read transactions

A technique is provided for automatically bypassing a transaction order queue for read completion transactions. The technique incorporates logic within an ASIC bridge, wherein read completion transactions are designated a relaxed ordering attribute value. Logic within the ASIC facilitates the read transactions by bypassing the transaction order queue if the relaxed ordering attribute is set accordingly. Similarly, the logic disables the attribute and enqueues the read completion transaction into the transaction order queue, if the relaxed ordering attribute is set to logical zero.

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Houston, TX, United States of America

Paras A Shah