National Semiconductor Corporation

Rambus Inc.

Samsung Electronics Co., Ltd.

Raytheon Company

Sundstrand Corporation

Silicon Pipe, Inc.

Para K Segaram

Joseph Charles Fjelstad

Belgacem Haba

Roy Thomas Myers, Jr

William F Wiedemann

Shu-Ing Ju

Charles L Vinn

Thomas J Obenhuber

An assembly for conducting an electronic signal. The assembly includes a substrate and an electronic cable. The substrate has distinct first and second regions to enable connection to first and second circuit boards, respectively. First and second through-holes are formed in the substrate in the first and second regions, respectively. The electronic cable is disposed within the first through-hole and extends out of the first through hole, adjacent the substrate and into the second through-hole.

Cabled signaling system and components thereof

A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.

Direct-connect signaling system

In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.

High-speed communication system with a feedback synchronization loop

High speed communication system with a feedback synchronization loop

Direct-connect integrated circuit signaling system for bypassing intra-substrate printed circuit signal paths

A repeater interface controller (&ldquo;RIC&rdquo;) integrated circuit with integrated filters and buffer drivers is provided for use in a repeater. In one embodiment, the RIC uses two filters to filter link pulse signals and data signals for a plurality of ports. Thus, the RIC is able to concurrently provide filtered link pulses to some ports and filtered data signals to other ports. Further, because only two filters are used, the area required to implement the plurality of ports is reduced relative to conventional repeaters that use a filter for each port. In another embodiment of the present invention, a RIC includes a logic circuit and a plurality of analog multiplexers and twisted pair buffer drivers. The analog multiplexers receive signals on their input lines and select which of these signals are passed to the buffer drivers to be outputted. The logic circuit provides control signals to the analog multiplexers such that the analog multiplexers select a new input line when the signal on the new input line is approximately the same as the signal on the currently selected input line. As a result, the signal passed on to the buffer drivers remains approximately the same, thereby reducing switching noise.

Integrated twisted pair filter with a secure RIC function

A repeater interface controller ('RIC') integrated circuit with integrated filters and buffer drivers is provided for use in a repeater. In one embodiment, the RIC uses two filters to filter link pulse signals and data signals for a plurality of ports. Thus, the RIC is able to concurrently provide filtered link pulses to some ports and filtered data signals to other ports. Further, because only two filters are used, the area required to implement the plurality of ports is reduced relative to conventional repeaters that use a filter for each port. In another embodiment of the present invention, a RIC includes a logic circuit and a plurality of analog multiplexers and twisted pair buffer drivers. The analog multiplexers receive signals on their input lines and select which of these signals are passed to the buffer drivers to be outputted. The logic circuit provides control signals to the analog multiplexers such that the analog multiplexers select a new input line when the signal on the new input line is approximately the same as the signal on the currently selected input line. As a result, the signal passed on to the buffer drivers remains approximately the same, thereby reducing switching noise.

The waveshaping functions provided by a summing resistor network and filter are performed by a waveshaping circuit that can be integrated with transceiving functions within a single integrated circuit. The waveshaping circuit utilizes the edges of an oscillator signal to generate a series of pairs of logic signals which have a defined timing relationship with respect to an input data signal. Each pair of logic signals is then utilized by a corresponding number of current stages to provide both an incremental portion of an output waveform and an incremental portion of a complementary output waveform. The pair of output waveforms can then be produced by summing together all of the incremental portions of the pair of waveforms.

Enhanced integrated waveshaping circuit

A waveshaping circuit, which includes a phase-lock-loop stage, an input logic stage, a delayed input logic stage, and a weighted current sum stage, shapes and filters a data signal to be transmitted onto the twisted-pair media of a local area network. The phase-lock-loop stage generates a series of incrementally-delayed timing signals in response to an oscillator signal. The input logic stage generates a plurality of pairs of logic signals by periodically latching a logic state and an inverse logic state of the data signal in response to the incrementally-delayed timing signals. The delayed input logic stage generates a plurality of pairs of delayed logic signals by periodically latching a logic state and an inverse logic state of an inverse data signal in response to the incrementally-delayed timing signals. The weighted current sum stage incrementally generates both an output data signal and a complementary output data signal in response to both the plurality of logic signals and the plurality of delayed logic signals.

Integrated waveshaping circuit using weighted current summing

A differential output stage utilizes four unity-gain differential amplifiers to receive a pair of input signals and to generate a differential signal. The non-inverting inputs of two of the differential amplifiers are connected together to receive one of the input signals while the outputs of the two differential amplifiers are connected to a forward node and to the inverting inputs of the two differential amplifiers. The non-inverting inputs of the remaining two differential amplifiers are connected together to receive the remaining input signals while the outputs of the remaining two differential amplifiers are connected to a reverse node and to the inverting inputs of the remaining two differential amplifiers. When an external resistor is connected between the forward node and the reverse node, the differential output stage drives a current across the external resistor in one direction when the difference between the amplitudes of the input signals is positive and drives a current across the external resistor in an opposite direction when the difference between the amplitudes of the input signals is negative.

Differential output stage with reduced idle current

A precision amplifier that, in response to digital inputs, zeros its offset voltage. The precision amplifier comprises a traditional amplifier; a current source controlled by a counter; a comparator; test switches; and control logic. A digital input, such as might be generated from a microprocessor, initiates the offset adjustment. The test switches disconnect the amplifier inputs from external package connections and connect the inputs together. The counter begins to count, changing the current produced by the current source at each count. The current from the current source is applied to the offset adjust circuit of the amplifier which changes the offset voltage as the current changes. The counter counts until the comparator indicates the offset voltage has been zeroed. Alternative embodiments allow the precision amplifier to adjust for offset introduced by circuitry connected to the input and the output of the precision amplifier.

Self-zeroing amplifier

A tunable filter (66) having a filter characteristic tracking an input signal in accordance with the invention includes a signal source (18) providing a variable frequency signal to be tracked by the filter characteristic; a frequency detector (62) coupled to the signal source for producing a detector output signal which is a function of the frequency of the variable frequency signal; a switching signal generator (64), responsive to the frequency detector output signal, for generating at least one switching signal having a variable frequency proportional to the detector output signal; a first capacitor (112, 126, 150, 152, 156 and 158) having a first terminal coupled to a reference potential and a second terminal; and a first switching circuit (114, 128, 154 and 160) having an input coupled to the variable frequency signal, responsive to the at least one switching signal, and in response to changes in level of the at least one switching signal alternately connecting the input of the first switching circuit to the second terminal of the first capacitor and the second terminal of the first capacitor to the output of the first switching circuit coupled to an output of the filter.

Growing community of inventors

Campbell, CA, United States of America

Para K Segaram